Systems and methods for decoding compressed data

• US 6,504,496 B1
• Filed: 04/10/2001
• Issued: 01/07/2003
• Est. Priority Date: 04/10/2001
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Rao, Raghunath Krishna, Hemkumar, Nariankadu Datareya, Deo, Sachin Sunil, Dokic, Miroslav, Mesarovic, Vladimir
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/832,290
• Time in Patent Office: 637 Days
• Field of Search: 341/106, 341/107, 341/67, 341/87, 707/10, 707/1, 707/3, 707/203
• US Class Current: 341/106
• CPC Class Codes: H03M 7/00 Conversion of a code where information is represented by a given sequence or number of digits to a code where the same , similar or subset of information is represented by a different sequence or number of digits

Abstract

A method of decoding an encoded bitstream. The method includes performing a two-table lookup. A first table is addressed in response to a first plurality of bits from the bitstream. An address into a second table is generated using a value in an entry in said first table accessed in the addressing step. A value (representing the decoded value corresponding to the codeword in the bitstream) in an entry in said second table at the address from the generating step is output.

Claims

1. A bitstream decoding method comprising the step of:

performing a two-table lookup, said two-table lookup comprising the steps of;

addressing a first table in response to a first plurality of bits from said bitstream; and

generating an address into a second table using a first value in an entry in said first table accessed in said addressing step; and

outputting a second value contained in an entry in said second table at said address from said generating step.

2. The method of claim 1 wherein said step of generating said address comprises the steps of:

retrieving said first value from a first portion of said entry in said first table; and

offsetting said first value by a third value represented by an additional number of bits in said bitstream.

3. The method of claim 2 wherein said step of generating said address further comprises the steps of:

retrieving a third value from a second portion of said entry in said first table; and

extracting said additional number of bits from said bitstream, wherein said additional number of bits corresponds to said third value.

4. The method of claim 2 wherein said second value contained in said entry in said second table is contained in a first portion of said entry in said second table, and wherein said two-table lookup further comprises the steps of:

retrieving a fifth value from a second portion of said entry in said second table; and

returning to said bitstream a number of bits from said first plurality of bits corresponding to a difference between a number of bits in said first plurality of bits and said fifth value.

5. The method of claim 1 further comprising the step of:

selecting a decoding process from a predetermined set of decoding processes in response to a code descriptor obtained from a portion of said bitstream, said set of decoding processes including said two-table lookup.

6. The method of claim 5 wherein said set of decoding processes further includes a binary search process.

7. The method of claim 1 wherein said first table comprises a plurality of entries, each entry of said plurality of entries comprising a first portion for holding a base address and a second portion holding a value representing a number of additional bits to be extracted from said bitstream.

8. The method of claim 1 wherein said second table comprises a plurality of entries, each entry of said plurality of entries comprising a first portion for holding an output value and a second portion for holding a length of a codeword representing an encoding of said output value.

9. A signal processing system comprising:

an input port configured to receive an encoded digital signal; and

a processor, including;

a first table;

a second table; and

a decoder, coupled to said first and second tables, configured to decode said encoded digital signal;

wherein said decoder comprises;

circuitry configured to address an entry in said first table in response to a plurality of bits in a bitstream of said encoded digital signal;

circuitry configured to generate an address into said second table in response to a value in a first portion of said entry in said first table; and

circuitry configured to output a value in a first portion of an entry in said second table, said entry corresponding to said address, said value representing a decoded value of a codeword in said encoded digital signal.

10. The system of claim 9 wherein said circuitry configured to generate said address into said second table includes:

circuitry configured to retrieve said value in said first portion of said entry in said first table; and

circuitry configured to offset said value in said first portion of said entry by a value of an additional number of bits in said bitstream.

11. The system of claim 10 wherein said circuitry configured to generate said address into said second table further includes:

circuitry configured to retrieve a value in a second portion of said entry in said first table; and

circuitry configured to extract said additional number of bits in response to said value in said second portion of said entry in said first table.

12. The system of claim 10 wherein said decoder further comprises circuitry configured to return a number of bits to said bitstream corresponding to a difference between a value in a second portion of said entry in said second table and said number of additional bits.

13. The system of claim 9 further comprising a memory, wherein at least a portion of said memory comprises memory for storing said first table and said second table.

14. The system of claim 9 wherein said circuitry configured to address an entry in said first table, said circuitry configured to generate an address into said second table, and circuitry configured to output a value in a first portion of an entry in said second table comprises circuitry for performing a first decode process, and wherein said decoder further comprises circuitry configured to select, in response to a code descriptor in a portion of said bitstream, between said circuitry for performing said first decode process and circuitry configured to perform a second decode process.

15. The system of claim 14 wherein said second decode process comprises a binary search process.

16. The system of claim 9 wherein said first table comprises a plurality of entries, each entry of said plurality of entries comprising a first portion for holding a base address and a second portion for holding a value representing a number of additional bits to be extracted from said bitstream.

17. The system of claim 9 wherein said second table comprises a plurality of entries, each entry of said plurality of entries comprising a first portion for holding an output value and a second portion for holding a length of a codeword representing an encoding of said output value.

18. A bitstream decoding method comprising the step of:

selecting a decoding process from a predetermined set of decoding processes in response to a current codebook used to encode said bitstream; and

decoding said bitstream using said decoding process from said selecting step.

19. The method of claim 18 wherein said set of decoding processes includes a two-table lookup process.

20. The method of claim 19 wherein said set of decoding processes further includes a binary search process, a linear search process and a single table lookup process.

21. The method of claim 19 wherein said decoding process is selected in response to a code descriptor in a portion of said bitstream.

22. The method of claim 18 wherein a current codebook is one of an Advanced Audio enCoding (AAC) Huffman codebook 10 (HCB_10) and an AAC Huffman codebook 11 (HCB_11) and wherein said decoding process from said selecting step comprises a two-table lookup process.

23. A signal processing system comprising:

an input port configured to receive an encoded digital signal; and

a decoder, configured to decode said encoded digital signal;

wherein said decoder comprises;

circuitry configured for selecting a decoding process from a predetermined set of decoding processes in response to a current codebook used to encode said bitstream; and

circuitry configured for decoding said bitstream using said decoding process from said selecting step.

24. The system of claim 23 wherein said set of decoding processes includes a two-table lookup process.

25. The system of claim 24 set of decoding processes further includes a binary search process, a linear search process and a single table lookup process.

26. The system of claim 23 wherein said decoder further comprises circuitry configured to select said decoding process in response to a code descriptor in a portion of said bitstream.