High-density low-cost read-only memory circuit

• US 6,504,746 B2
• Filed: 05/31/2001
• Issued: 01/07/2003
• Est. Priority Date: 05/31/2001
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Ku, Joseph Weiyeh
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/871,504
• Publication Number:
  US 20020184433A1
• Time in Patent Office: 586 Days
• Field of Search: 365/51, 365/52, 365/94, 365/105, 365/103, 365/63
• US Class Current: 365/94
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.

Claims

1. A memory circuit, comprising:

a passive device chip, including only passive devices configured to form a read-only memory array; and

an active device chip, having supporting circuitry electrically coupled to the memory array, where the passive device chip is not stacked on the active device chip and where the supporting circuitry for the read-only memory array is external to the passive device chip.

2. The circuit of claim 1, wherein the passive devices include:

amorphous-Silicon diodes.

3. The circuit of claim 1, wherein the passive devices include:

poly-Silicon diodes.

4. The circuit of claim 1, wherein the passive chip and the active chip are coupled together with bond wires.

5. The circuit of claim 1, wherein the supporting circuitry includes:

bit-line circuitry; and

word-line circuitry.

6. The circuit of claim 5, wherein the supporting circuitry further includes:

an address decoder;

a sense amplifier; and

an output driver.

7. The circuit of claim 1, wherein the memory array comprises:

a first memory array; and

a second memory array, deposited upon the first memory array layer.

8. The memory circuit of claim 7, wherein the second memory array can be stacked on top of the memory array.

9. The circuit of claim 8, further comprising:

a second passive device chip, coupled to the multi-chip module and the active chip.

10. The circuit of claim 9, wherein the second passive device chip includes:

a second read-only memory array electrically coupled to the supporting circuitry.

11. The circuit of claim 1, further comprising:

a multi-chip module, to which the passive chip and the active chip are physically coupled.

13. The memory circuit of claim 1, wherein the passive device chip is separate from the active device chip.

12. A memory circuit, comprising:

a passive device chip, including only passive devices, including amorphous-Silicon diodes, configured to form a read-only memory array;

an active device chip, having supporting circuitry electrically coupled to the memory array with bond wires, where the passive device chip is not stacked on the active device chip and where the supporting circuitry for the read-only memory array is external to the passive device chip; and

a multi-chip module, to which the passive chip and the active chip are physically coupled.

14. The memory circuit of claim 12, wherein the passive device chip is separate from the active device chip.