Method and apparatus for discharging memory array lines

• US 6,504,753 B1
• Filed: 06/29/2001
• Issued: 01/07/2003
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Crowley, Matthew P.
• Primary Examiner(s): Nelms; David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/897,784
• Time in Patent Office: 557 Days
• Field of Search: 365/94,100,103,104,105,171,173,175,207,71,159,189.09,189.07,148,243
• US Class Current: 365/175
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A passive element memory array preferably biases selected X-lines to an externally received V_PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V_PP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V_PP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V_PP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Claims

1. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, said integrated circuit having an operating mode biasing a group of at least one unselected Y-line at a different voltage than a group of at least one unselected X-line, a method of bringing each line of the Y-line group and each line of the X-line group to a particular voltage, said method comprising the steps of:

coupling each line of the Y-line group to each line of the X-line group so that the respective voltages of each such coupled together line are brought toward an intermediate voltage between the first and second voltages; and

coupling at least one of such coupled together lines to a node conveying the particular voltage so that the respective voltages of each such coupled together line are brought to the particular voltage.

2. A method as recited in claim 1 wherein the first coupling step comprises:

coupling each respective line of the Y-line group through a respective Y-line driver to a common node serving each respective Y-line driver;

coupling each respective line of the X-line group through a respective X-line driver to a common node serving each respective X-line driver; and

coupling the Y-line driver common node to the X-line driver common node.

3. A method as recited in claim 2 further comprising:

removing a source of the first voltage previously coupled to the Y-line driver common node before coupling the Y-line driver common node to the X-line driver common node; and

removing a source of the second voltage previously coupled to the X-line driver common node before coupling the Y-line driver common node to the X-line driver common node.

4. A method as recited in claim 1 wherein the second coupling step comprises:

at least coupling one of the X-line driver common node and the Y-line driver common node to the particular voltage node whose respective voltage is already closer to the particular voltage.

5. A method as recited in claim 1 wherein the second coupling step comprises:

coupling both the X-line driver common node and Y-line driver common node to the particular voltage node.

6. A method as recited in claim 1 wherein:

the particular voltage is substantially equal to one of the respective voltages to which the group of X-lines and the group of Y-lines are initially biased.

7. A method as recited in claim 1 wherein:

the particular voltage is different than both of the respective voltages to which the group of X-lines and the group of Y-lines are initially biased.

8. A method as recited in claim 1 wherein:

the particular voltage comprises a ground reference voltage.

9. A method as recited in claim 1 wherein the second coupling step comprises:

coupling at least one of the X-line driver common node and Y-line driver common node to the particular voltage node.

10. A method as recited in claim 1 wherein:

the group of at least one unselected Y-line includes some but not all of the unselected Y-lines in the array.

11. A method as recited in claim 1 wherein:

the group of at least one unselected Y-line includes all of the unselected Y-lines in the array.

12. A method as recited in claim 1 further comprising:

deselecting any previously-selected Y-line before the first coupling step, thereby resulting in all Y-lines of the array being unselected during the first coupling step; and

deselecting any previously-selected X-line before the first coupling step, thereby resulting in all X-lines of the array being unselected during the first coupling step.

13. A method as recited in claim 1 wherein:

the memory cells comprise write-once anti-fuse memory cells.

14. A method as recited in claim 1 wherein:

the memory cells comprise write-once fuse memory cells.

15. A method as recited in claim 1 wherein:

each memory cell comprises a layer of organic material having a resistance that is switched to a lower or higher state by application of a voltage across the layer.

16. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of discharging a group of at least one unselected X-line and a group of at least one unselected Y-line, said group of at least one unselected X-line previously biased at a voltage different than that of said group of at least one unselected Y-line, said method comprising the steps of:

sharing charge between the group of unselected Y-lines and the group of unselected X-lines, thereby tending to bring the respective voltage of each such unselected Y-line and the respective voltage of each such unselected X-line closer together in magnitude, and consequently reducing a respective voltage impressed across each unselected memory cell respectively coupled therebetween; and

discharging the group of unselected Y-lines and the group of unselected X-lines to an inactive voltage.

17. A method as recited in claim 16 wherein the discharging step comprises:

coupling one of the group of unselected X-lines and the group of unselected Y-lines to the inactive voltage;

wherein the other of the group of unselected X-lines and group of unselected Y-lines is discharged to the inactive voltage by charge sharing between the group of unselected Y-lines and the group of unselected X-lines.

18. A method as recited in claim 16 wherein the discharging step comprises:

coupling both the group of unselected X-lines and the group of unselected Y-lines to the inactive voltage.

19. A method as recited in claim 16 wherein:

the inactive voltage comprises a ground reference voltage.

20. A method as recited in claim 16 wherein:

the discharging step is initiated substantially at the same time as the charge sharing step is initiated.

21. A method as recited in claim 16 further comprising:

deselecting any previously-selected one or more Y-lines and any previously-selected one or more X-lines either before or during the charge sharing step.

22. A method as recited in claim 16 wherein:

the discharging step is initiated substantially after the charge sharing step is initiated.

23. A method as recited in claim 22 further comprising:

initiating the discharging step a predetermined delay after initiating the charge sharing step.

24. A method as recited in claim 22 further comprising:

initiating the discharging step a variable delay after initiating the charge sharing step based upon determining a degree of charge sharing completeness.

25. A method as recited in claim 22 further comprising:

sensing at least one signal representative of the unselected Y-line voltages and at least one signal representative of the unselected X-line voltages to determine when the respective voltage difference therebetween falls within a certain range; and

initiating the discharging step after determining that the respective voltage difference therebetween falls within the certain range.

26. A method as recited in claim 25 wherein:

the discharging step is initiated after the voltage impressed across each of said unselected memory cells has been reduced to within about 1.0 volt.

27. A method as recited in claim 25 wherein:

the discharging step is initiated after the voltage impressed across each of said unselected memory cells is less than a voltage difference between the inactive voltage and one of the group of unselected X-lines and the group of unselected Y-lines.

28. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of discharging the array comprising the steps of:

discharging inter-line capacitance between the unselected X-lines and the unselected Y-lines by coupling each unselected Y-line to each unselected X-line; and

discharging stray capacitance on the unselected X-lines and unselected Y-lines by coupling at least the unselected X-lines or the unselected Y-lines to a ground reference node.

29. A method as recited in claim 28 wherein:

the stray capacitance discharging step is initiated substantially after the inter-line discharging step is initiated.

30. A method as recited in claim 28 wherein:

the stray capacitance is discharged by the stray capacitance discharging step at a slower rate than the inter-line capacitance is discharged by the inter-line capacitance discharging step.

31. A method as recited in claim 30 wherein:

the stray capacitance discharging step is initiated before the inter-line capacitance discharging step is completed.

32. A method as recited in claim 31 wherein:

the stray capacitance discharging step is initiated at about the same time as the first discharging step is initiated.

33. In an integrated circuit including an array of write-once passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, said integrated circuit having a write mode which biases a group of unselected Y-lines at an unselected Y-line voltage (UYL voltage) and which biases a group of unselected X-lines at an unselected X-line voltage (UXL voltage) that is different than the UYL voltage, a method of discharging each line of the Y-line group and each line of the X-line group comprising the steps of:

(a) coupling each respective line of the Y-line group through a respective Y-line driver to an unselected Y-line bias node (UYL bias node) for the Y-line drivers;

(b) coupling each respective line of the X-line group through a respective X-line driver to an unselected X-line bias node (UXL bias node) for the X-line drivers;

(c) coupling the UYL bias node to the UXL bias node; and

(d) coupling at least one of the UYL bias node and the UXL bias node to a ground reference node.

34. A method as recited in claim 33 wherein step (d) comprises:

coupling both the UYL bias node and the UXL bias node to the ground reference node.

35. A method as recited in claim 33 wherein:

step (d) is initiated substantially before step (c) is initiated.

36. A method as recited in claim 33 wherein:

step (d) is initiated at about the same time as step (c) is initiated.

37. A method as recited in claim 33 wherein:

step (d) is initiated substantially after step (c) is initiated.

38. A method as recited in claim 37 wherein:

step (d) is initiated a predetermined delay after step (c) is initiated.

39. A method as recited in claim 33 wherein:

steps (a) and (b) are each initiated substantially before either step (c) or step (d) is initiated.

40. A method as recited in claim 33 wherein:

one of the UXL voltage and the UYL voltage is equal to the ground reference node voltage.

41. A method as recited in claim 33 wherein:

both the UXL voltage and the UYL voltage are different than the ground reference node voltage.

42. A method as recited in claim 33 further comprising:

removing a source of the UYL voltage previously coupled to the UYL bias node, and removing a source of the UXL voltage previously coupled to the UXL bias node, all before initiating step (c).

43. A method as recited in claim 33 further comprising:

deselecting any previously-selected one or more Y-lines and any previously-selected one or more X-lines, all before initiating step (c).

44. In an integrated circuit including at least one memory sub-array of passive element memory cells arranged in at least two memory planes, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, a method of discharging a particular sub-array comprising the steps of:

coupling together, by way of one or more intermediate nodes, each of a respective group of X-lines associated with each respective memory plane within the particular sub-array, and each of a respective group of Y-lines associated with each respective memory plane within the particular sub-array, to discharge inter-line array capacitance existing therebetween; and

coupling at least one of the one or more intermediate nodes to a ground reference node, to discharge stray capacitance existing on the coupled-together X-lines and Y-lines.

45. A method as recited in claim 44 wherein:

a respective group of X-lines and a respective group of Y-lines associated with at least a first respective memory plane are previously biased to voltages different from the ground reference; and

a respective group of X-lines and a respective group of Y-lines associated with at least a second respective memory plane are previously floating.

46. A method as recited in claim 44 wherein:

the respective group of X-lines and the respective group of Y-lines associated with a first respective memory plane are previously biased to voltages different from the ground reference; and

all other respective groups of X-lines and all other respective groups of Y-lines not associated with the first respective memory plane are previously floating.

47. An integrated circuit comprising:

an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines;

means for biasing a group of at least one unselected Y-line at a voltage different than that of a group of at least one unselected X-line when in a write mode;

a first coupling circuit for coupling the group of unselected Y-lines to the group of unselected X-lines, for driving the respective voltages of each such coupled together line closer toward a single voltage; and

a second coupling circuit for coupling the group of at least one unselected Y-line and the group of at least one unselected X-line to an inactive voltage.

48. A circuit as recited in claim 47 wherein the means for biasing comprises:

a plurality of X-line driver circuits for biasing unselected X-lines to a first voltage during the write mode;

a plurality of Y-line driver circuits for biasing unselected Y-lines to a second voltage different than the first voltage during the write mode.

49. An integrated circuit comprising:

at least one memory sub-array of passive element memory cells arranged in at least two memory planes, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array;

for each memory plane within each sub-array, said integrated circuit further comprising

first means for biasing unselected X-lines associated with the memory plane of the sub-array at a different voltage than unselected Y-lines associated with the memory plane of the sub-array, when in a write mode;

second means for coupling unselected X-lines associated with the memory plane of the sub-array to unselected Y-lines associated with the memory plane of the sub-array; and

third means for coupling to a ground reference node the coupled-together unselected X-lines and unselected Y-lines associated with the memory plane of the sub-array.

50. The integrated circuit as recited in claim 49 wherein, for each sub-array, the integrated circuit further comprises:

means for coupling unselected X-lines or Y-lines associated with one memory plane of the sub-array to unselected X-lines or Y-lines associated with at least one other memory plane of the sub-array.

51. The integrated circuit as recited in claim 49 wherein:

the third means comprises at least a conductive path between the ground reference node and one of the coupled-together X-lines and the coupled-together Y-lines;

wherein the other of the coupled-together X-lines and the coupled-together Y-lines is coupled to the ground reference node through the second means.