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Method and apparatus for discharging memory array lines

  • US 6,504,753 B1
  • Filed: 06/29/2001
  • Issued: 01/07/2003
  • Est. Priority Date: 03/21/2001
  • Status: Expired due to Term
First Claim
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1. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, said integrated circuit having an operating mode biasing a group of at least one unselected Y-line at a different voltage than a group of at least one unselected X-line, a method of bringing each line of the Y-line group and each line of the X-line group to a particular voltage, said method comprising the steps of:

  • coupling each line of the Y-line group to each line of the X-line group so that the respective voltages of each such coupled together line are brought toward an intermediate voltage between the first and second voltages; and

    coupling at least one of such coupled together lines to a node conveying the particular voltage so that the respective voltages of each such coupled together line are brought to the particular voltage.

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