Resistive cross point memory with on-chip sense amplifier calibration method and apparatus

• US 6,504,779 B2
• Filed: 05/14/2001
• Issued: 01/07/2003
• Est. Priority Date: 05/14/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Perner, Frederick A.
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US09/855,118
• Publication Number:
  US 20020167838A1
• Time in Patent Office: 603 Days
• Field of Search: 365/173, 365/158, 365/129, 365/209, 365/189.01
• US Class Current: 365/209
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A resistive cross point memory (RXPtM) cell array device, one example of which is a magnetic random access memory (MRAM) device, includes a chip on which is formed an array of RXPtM cells, an array of sense amplifiers used in sensing resistance values of the RXPtM cells, and an input/output (I/O) controller. The I/O controller includes a calibration controller, which tests the combination of a particularly selected memory cell and a particular associated one of the array of sense amplifiers in view of then existing environmental conditions, to assure that the sense amplifier has an acceptable calibration. Data integrity of the RXPtM cell array device is assured by a method in which each operation to sense data from the device includes a calibration test, which if not passed results in the sense amplifiers being recalibrated. When proper calibration of the sense amplifies is indicated, then sensing of the data value proceeds.

Claims

1. A resistive cross point memory (RXPtM) device which is responsive to environmental factors including temperature and operating voltage, said device comprising:

plural RXPtM cells, each of said RXPtM cells including a pair of magnetic layers one of which is fixed in magnetic orientation, and the other of which is variable in magnetic orientation;

a resistive layer interposed between said pair of magnetic layers, so that each of said plural RXPtM cells has a characteristic resistance dependent upon the respective magnetic orientation of said other magnetic layer;

a grid of conductors crossing one another at and electrically connecting to respective ones of said pair of magnetic layers of said plural RXPtM cells;

a variable-calibration sense amplifier associated with said plural RXPtM cells to sense the resistance of a selected one of said cells; and

a calibration controller associated with both said plurality of RXPtM cells and with said sense amplifier, so as to test the calibration of said sense amplifier for sensing selected RXPtM cell in view of existing environmental factors.

2. The RXPtM cell array of claim 1, further including a single substrate, said single substrate carrying all of:

said RXPtM cell array;

said variable-calibration sense amplifier; and

said calibration controller, which calibration controller includes an integrator with a capacitor, a comparator, and a pre-settable counter.

3. The circuit of claim 2, wherein said calibration controller includes circuit means for applying a constant voltage to a selected one of said plurality of RXPtM cells and to said integrator, said comparator receiving a time-variant capacitor discharge voltage signal from said capacitance and outputting a signal indicative of discharging of said capacitor to a selected voltage level, a switching junction switching between a conductive and a nonconductive state dependent upon the value of said outputted comparator signal, a clock generating clock count pulses, and said pre-settable counter receiving clock count pulses from said source via said switching junction while said switching junction is conductive.

4. In a RXPtM cell array device, a method of testing for needed recalibration of a sense amplifier which is utilized to sense a resistance value of a selected RXPtM cell of the array, and in view of present values of time-variant operating parameters of the RXPtM cell array, said method comprising steps of:

defining an average time value, which is indicative of averaged time values for each of a selected set of RXPtM cells, while the resistance of each cell of the selected set of cells is connected in series with a selected pre-charged capacitance, and with present operating parameters of the RXPtM cell array applying;

determining a time value, which is indicative of connection of the resistance of the selected RXPtM cell and said selected pre-charged capacitance in series;

comparing the time value to the average time value to determine a difference value; and

recalibrating the sense amplifier if the difference value exceeds a first determined range.

5. The method of claim 4, further comprising the step of ignoring the difference value and not recalibrating the sense amplifier, if the difference value exceeds the first determined range and also exceeds a second determined range.

6. A self-calibrating resistive cross point memory (RXPtM) cell array chip, said RXPtM cell array chip having a substrate upon which is defined an array of plural memory cells, an array of sense amplifiers each associated with a group of the memory cells of the array of plural memory cells, and circuit means for testing validity of data sensing from each of said memory cells via the associated sense amplifier;

said chip comprising in combination;

a substrate;

a rectangular array of plural RXPtM cells defined on said substrate, each of said RXPtM cells including a pair of magnetic layers and having a resistance value dependent upon the relative direction of magnetization of said pair of magnetic layers;

a grid of conductive word and bit lines crossing one another at and electrically connecting to respective ones of said plural RXPTM cells of said array, said resistance value of each RXPtM cell of said array being connected between word and bit lines crossing at the respective memory cell;

an array of variable-calibration sense amplifiers formed upon said substrate, and each associated with plural ones of said plural RXPtM cells to sense the resistance of a selected one of said plural RXPtM cells; and

a calibration controller formed on said substrate and associated with both said array of RXPtM cells and with said array of sense amplifiers, so as to test an electrical connection of a selected one of the plural memory cells and a particular sense amplifier for acceptable calibration of the amplifier.

7. The memory chip of claim 6, wherein said calibration controller further includes an integrator with a capacitor, a comparator, and a pre-settable counter.

8. The memory chip of claim 7, wherein said calibration controller further includes a switch having connection to a source of controlled charging voltage for said capacitor, and when closed said switch conducting said controlled charging voltage to said capacitor to pre-charge said capacitor.

9. The memory chip of claim 7, wherein said integrator includes said precharged capacitor, and a resistive load selected from among said plural RXPtM cells.

10. The memory chip of claim 7, wherein said comparator includes a connection to s aid pre-charged capacitor, and a connection to a source of reference voltage.

11. The memory chip of claim 7, wherein said pre-settable counter includes a connection to said comparator via a switchable junction opening and closing under control of said comparator, and connection to a source of clock pulses via said switchable junction.

12. A method of operating a resistive cross point memory (RXPtM) cell array device;

said device including a plurality of memory cells and an sense amplifier connected to a selected one of said plurality of memory cells to sense a variable resistance value of the selected memory cell, which variable resistance value is indicative of a binary data value stored in the selected memory cell;

said sense amplifier having a settable calibration; and

apparent resistance of the selected memory cell also varying in response to time-variant environmental factors irrespective of a data value stored in the selected memory cell;

said method including steps of;

calibrating the sense amplifier;

utilizing a selected group of the plural memory cells to establish an average resistance value for a memory cell;

storing a data value in the selected memory cell;

in preparation to sensing the stored data value from the selected memory cell, testing apparent resistance of the selected memory cell with presently existing environmental factors, and if the apparent resistance is within a determined range of said average resistance value, then sensing the data value from the selected memory cell using the sense amplifier.

13. The method of claim 12 further including the steps of recalibrating the sense amplifier if the apparent resistance of the selected memory cell is outside of the determined range.

14. The method of claim 12 including the step of ignoring the selected memory cell and not recalibrating the sense amplifier if the apparent resistance of the selected memory cell is outside of the determined range and also outside of a second wider certain range from the average resistance value.

15. The method of claim 12 wherein said sensing step includes:

sensing the apparent resistance of said selected memory cell, and recording the apparent resistance value;

writing either a binary zero or binary one to the selected memory cell, sensing the associated resistance of the memory cell, and recording the associated resistance value;

writing the other of a binary zero or binary one to the selected memory cell, sensing the respective resistance of the memory cell, and recording the respective resistance value;

comparing the apparent resistance value to both of said associated resistance value and to said respective resistance value, and determining the identity of the stored data value according to a minimum difference; and

writing the identified data value to the selected memory cell.

16. The method of claim 12 including the step of sensing the apparent resistance value of the selected memory cell after recalibrating the sense amplifier.

17. A resistive magnetic memory cell array device, said memory cell array device being responsive to time-variant environmental factors including temperature and operating voltage to vary an apparent resistance of memory cells of the device, said device comprising in combination:

an array of plural memory cells, each of said memory cells including a spin dependent resistive layer the resistance of which is dependent upon the magnetic fields applied by a pair of adjacent magnetic layers, one of said pair of magnetic layers being fixed in magnetic orientation, and the other of said pair of magnetic layers being variable in magnetic orientation between a parallel and an anti-parallel orientation relative to said fixed layer, each of said memory cells having one of two characteristic resistance values dependent upon the magnetic orientation of said other magnetic layer so as to store binary data values;

a grid of conductive word and bit lines crossing one another at and electrically connecting to respective ones of said plural memory cells of said array;

an array of variable-calibration sense amplifiers each associated with plural ones of said plural memory cells to sense the characteristic resistance of a selected one of said plural memory cells; and

a calibration controller associated with both said array of memory cells and with said array of sense amplifiers, so as to test the apparent resistance of a particular memory cell with presently existing environmental factors of temperature and operating voltage applying.

18. A resistive cross point memory (RXPtM) device which is responsive to environmental factors including temperature and operating voltage, said device comprising:

plural RXPtM cells, each of said RXPtM cells including a pair of magnetic layers one of which is fixed in magnetic orientation, and the other of which is variable in magnetic orientation;

a resistive layer interposed between said pair of magnetic layers;

each of said plural RXPtM cells having a characteristic resistance dependent upon the respective magnetic orientation of said other magnetic layer;

a grid of row conductors and column conductors crossing one another at and electrically connecting to respective ones of said pair of magnetic layers of said plural RXPtM cells;

a variable-calibration sense amplifier associated with said plural RXPtM cells to sense the resistance of a selected one of said cells; and

a calibration controller associated with both said plurality of RXPtM cells and with said sense amplifier, so as to test the calibration of said sense amplifier for sensing selected RXPtM cell in view of existing environmental factors;

said calibration controller including an integrator, a comparator, and a pre-settable counter.

19. The resistive cross point memory (RXPtM) device of claim 18, wherein said calibration controller further includes a capacitor, and a switch having connection to a source of controlled charging voltage for said capacitor, and when closed said switch conducting said controlled charging voltage to said capacitor to pre-charge said capacitor.

20. The resistive cross point memory (RXPtM) device of claim 18, wherein said integrator includes said pre-charged capacitor, and a resistive load selected from among said plural RXPtM cells.

21. The resistive cross point memory (RXPtM) device of claim 18, wherein said comparator includes a connection to said pre-charged capacitor, and a connection to a source of reference voltage.

22. The resistive cross point memory (RXPtM) device of claim 18, wherein said pre-settable counter includes a connection to said comparator via a switchable junction opening and closing under control of said comparator, and connection to a source of clock pulses via said switchable junction.