Method of testing an evaluation circuit

• US 6,505,136 B1
• Filed: 05/17/2000
• Issued: 01/07/2003
• Est. Priority Date: 05/19/1999
• Status: Expired due to Fees

• Current Assignee: Nokia Solutions and Networks US LLC (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Pieper, Norbert, Zimmermann, Wolfgang
• Primary Examiner(s): Hilten, John S.
• Assistant Examiner(s): Cherry, Stephen J.
• Application Number:
  US09/572,612
• Time in Patent Office: 965 Days
• Field of Search: 702/117, 324/422
• US Class Current: 702/117
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

The invention concerns a method of testing an evaluation circuit (10 11), which checks the correct contact of a switch (13) with a testing means (14) in a d.c.-supplied circuit. The testing means (14) includes for example a capacitor (15) in parallel with the switch (13). The evaluation circuit (10) itself is made up of a controller (11), an input and an output buffer (17 18). To determine faulty conditions in the output buffer (17), the invention arranges that when testing for faults both the input and the output buffer (17 18) be actively connected by connecting them connected to the controller (11) via a respective data line (21 21a) for exchanging data.

Claims

1. An evaluation circuit (10) for checking for the presence of a switch or key (13) in a d.c. circuit, comprising:

a testing means (14) connected with the switch or key (13) to form a unit (12) having first and second terminals;

an I/O port (16) connected to-one terminal of the unit (12);

an input buffer (18) connected to the I/O port (16) for measuring the voltage at the I/O port (16);

an output buffer (17) controllably connected to the I/O port (16);

a charging resistor (R1) in series with the testing means (14) and also connected to a d.c. voltage source providing a source voltage (V+); and

a microcomputer (11) for controlling the operation of the output buffer (17);

wherein the microcomputer (11) controls the evaluation circuit (10) to determine the presence of the switch or key (13) in the d.c. circuit and the status of the output buffer (17) by performing the following operations.

1) at time 1, determining the voltage at the I/O port (16);

2) at time 2, controllably connecting the output buffer (17) to the I/O port (16) so as to cause the testing means (14) to be discharged within a discharge time period (t_u);

3) at time 5, determining the voltage at the I/O port (16), where time 5 occurs during the discharge time period (t_u);

4) at time 3, at the end of the discharge time period (t_u), controllably disconnecting the output buffer (17) from the I/O port (16) so as to allow the testing means (14) to charge to the source voltage (V+) via the charging resistor (R1); and

5) at time 4, during a charging time period (t_u) following the discharging time period (t_u), measuring the voltage at the I/O port (16), where the charging time period (t_m) is substantially less than the amount of time necessary for the testing means to become fully charged;

such that the presence of the switch or key (13) and the status of the output buffer (17) of the evaluation circuit (10) is 40 determined as follows;

if at time 1 the measured voltage is greater than a predetermined voltage (U_g) less than the source voltage (V+), and at time 4 the measured voltage is less than the predetermined voltage (U_g), then determining that the switch or key (13) is present and that the output buffer (17) is operating normally;

if the voltage measured at times 1, 5 and 4 are all greater than predetermined voltage (U_g), then determining that at least the output buffer (17) is faulty; and

if the measured voltage at times 1 and 4 are both greater than the predetermined voltage (U_g) and if the measured voltage at time 5 is less than predetermined voltage (U_g), then determining that the switch or key (13) is not present and that the output buffer (17) is operating normally.

2. A method by which a microcomputer (11) of an evaluation circuit (10) is operative for checking for the presence of a switch or key (13) in a d.c. circuit, the evaluation circuit (10) including;

a testing means (14) connected with the switch or key (13) to form a unit (12) having first and second terminals;

an I/O port (16) connected to one terminal of the unit (12);

an input buffer (18) connected to the I/O port (16) for measuring the voltage at the I/O port (16);

an output buffer (17) controllably connected to the I/O port (16);

a charging resistor (R1) in series with the testing means (14) and also connected to a d.c. voltage source providing a source voltage (V+); and

the microcomputer (11), for controlling the operation of the output buffer (17);

the method comprising the steps of;

1) at time 1, determining the voltage at the I/O port (16);

2) at time 2, controllably connecting the output buffer (17) to the I/O port (16) so as to cause the testing means (14) to be discharged within a discharge time period (t_u);

3) at time 5, determining the voltage at the I/O port (16), where time 5 occurs during the discharge time period (t_u);

4) at time 3, at the end of the discharge time period (t_u), controllably disconnecting the output buffer (17) from the I/O port (16) so as to allow the testing means (14) to charge to the source voltage (V+) via the charging resistor (R1); and

5) at time 4, during a charging time period (t_m) following the discharging time period (t_u), measuring the voltage at the I/0 port (16), where the charging time period (t_m) is substantially less than the amount of time necessary for the testing means to become fully charged;

and then determining the presence of the switch or key (13) and the status of the output buffer (17) of the evaluation circuit (10) according to the following rules;

if at time 1 the measured voltage is greater than a predetermined voltage (U_g) less than the source voltage (V+), and at time 4 the measured voltage is less than the predetermined voltage (U_g), then determining that the switch or key (13) is present and that the output buffer (17) is operating normally;

if the voltage measured at times 1, 5 and 4 are all greater than predetermined voltage (U_g), then determining that at least the output buffer (17) is faulty; and

if the measured voltage at times 1 and 4 are both greater than the predetermined voltage (U_g) and if the measured voltage at time s is less than predetermined voltage (U_g), then determining that the switch or key (13) is not present and that the output buffer (17) is operating normally.