Fail-over of multiple memory blocks in multiple memory modules in computer system

• US 6,505,305 B1
• Filed: 07/16/1998
• Issued: 01/07/2003
• Est. Priority Date: 07/16/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Information Technologies Group LP (HP Inc.)
• Inventors: Olarig, Sompong P.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US09/116,714
• Time in Patent Office: 1,636 Days
• Field of Search: 714/5, 714/6, 714/7, 714/8, 714/29, 714/42, 714/54, 714/718, 711/152, 711/151
• US Class Current: 714/5.11
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Claims

1. A computer system comprising:

a bus subsystem for transferring digital information;

a processing unit for processing the digital information;

a mass storage device for storing the digital information and cooperatively coupled to the bus subsystem to transmit and receive the digital information;

a memory module array having multiple memory modules, each of the memory modules having multiple memory blocks for storing the digital information transmitted or received by the mass storage device;

a memory controller for controlling transfer, between the bus subsystem, the processing unit and the memory module array, of the digital information transmitted or received by the mass storage device; and

a memory fail-over subsystem cooperatively coupled to fail-over individual memory blocks, and the digital information stored therein, of one or more of the memory modules; and

an error monitoring circuitry cooperatively coupled to transmit error data to the memory controller,

wherein the memory fail-over subsystem fails-over an individual memory block when the error data for the individual memory block exceeds a permissible threshold, and accesses to remaining memory blocks in the same memory module as the failed-over memory block are satisfied by the remaining memory blocks in the same memory module.

2. The computer system of claim 1 further comprising an auxiliary memory cooperatively coupled to receive the digital information intended for failed-over memory blocks, wherein accesses to individual failed-over memory blocks are satisfied by the auxiliary memory.

3. The computer system of claim 2 further comprising a tag storage having storage locations for storing tags identifying one or more failed-over memory blocks in one or more of the memory modules and pointing to a location in the auxiliary memory where the digital information intended for the failed-over memory blocks is stored.

4. The computer system of claim 3 further comprising a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block and cooperatively coupled to the memory controller to provide a hit signal thereto if the access is to a failed-over memory block.

5. The computer system of claim 1 further comprising:

a tag storage having storage locations for storing tags corresponding to one or more memory blocks in one or more of the memory modules;

wherein a tag corresponding to a failed-over memory block is stored in the tag storage upon fail-over of the failed-over memory block.

6. The computer system of claim 5 further comprising:

an auxiliary memory cooperatively coupled to the memory controller to respond to memory accesses;

wherein;

the digital information stored in a failed-over memory block in a memory module is transferred to an auxiliary location in the auxiliary memory; and

the tag corresponding to the failed-over memory block further corresponds to the auxiliary location for the transferred digital information.

7. The computer system of claim 6 wherein the auxiliary memory is an embedded memory in the memory controller.

8. The computer system of claim 6 wherein the auxiliary memory is external to the memory controller.

9. The computer system of claim 6 further comprising:

a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block by identifying a tag stored in the tag storage and cooperatively coupled to the memory controller to provide a hit signal thereto if the access is to a failed-over memory block;

wherein, when the tag look-up circuitry identifies a tag corresponding to the accessed memory block, the memory block access is satisfied by the auxiliary location corresponding to the identified tag.

10. The computer system of claim 1 further comprising:

an auxiliary memory cooperatively coupled to the memory controller to respond to memory accesses;

wherein the digital information stored in a failed-over memory block in a memory module is transferred to the auxiliary memory.

11. The computer system of claim 1 further comprising:

an error log for storing the transmitted error data;

wherein the error data stored in the error log is processed to determine whether the error data exceeds the permissible threshold.

12. A memory controller for controlling functions of multiple memory modules, each having multiple memory blocks, comprising

a fail-over circuitry for failing-over individual memory blocks in one or more of the memory modules;

and

an error monitoring circuitry receiving error data regarding errors in digital information returned from an accessed memory module,

wherein the memory fail-over subsystem fails-over an individual memory block when the error data for the individual memory block exceeds a permissible threshold, and accesses to the non-failed-over memory blocks are satisfied by the memory blocks in the memory modules.

13. The memory controller of claim 12 further comprising an auxiliary memory cooperatively coupled to receive digital information intended for failed-over memory blocks, wherein accesses to individual failed-over memory blocks are satisfied by the auxiliary memory.

14. The memory controller of claim 13 further comprising a tag storage having storage locations for storing tags identifying one or more failed-over memory blocks in one or more of the memory modules and pointing to a location in the auxiliary memory where the digital information intended for the failed-over memory blocks is stored.

15. The memory controller of claim 14 further comprising a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block and cooperatively coupled to the memory controller to provide a hit signal thereto if the access is to a failed-over memory block.

16. The memory controller of claim 12 further comprising:

a tag storage having storage locations for storing tags corresponding to one or more memory blocks in one or more of the memory modules;

wherein a tag corresponding to a failed-over memory block is stored in the tag storage upon fail-over of the memory block.

17. The memory controller of claim 16 further comprising:

an auxiliary memory capable of responding to memory accesses;

wherein;

the digital information stored in a failed-over memory block in a memory module is transferred to an auxiliary location in the auxiliary memory; and

the tag corresponding to the failed-over memory block further corresponds to the auxiliary location for the transferred digital information.

18. The memory controller of claim 17 wherein the auxiliary memory is an embedded memory in the memory controller.

19. The memory controller of claim 17 wherein the auxiliary memory is external to the fail-over circuitry.

20. The memory controller of claim 17 further comprising a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block, and providing a hit signal if the access is to a failed-over memory block, wherein the tag look-up circuitry identifies a tag corresponding to the failed-over memory block, and the memory block access is satisfied by the auxiliary location corresponding to the identified tag.

21. The memory controller of claim 12 further comprising an auxiliary memory responding to memory accesses, wherein the digital information stored in a failed-over memory block in a memory module is transferred to the auxiliary memory to satisfy subsequent memory accesses.

22. The memory controller of claim 12 further comprising an error log for storing the transmitted error data, wherein the error data stored in the error log is processed to determine whether the error data exceeds the permissible threshold.

23. A method of controlling accesses to multiple memory modules, each having multiple memory blocks, comprising the steps of:

monitoring errors in accesses to the memory blocks in relation to a permissible error threshold; and

upon detection of monitored errors for a particular memory block exceeding the permissible error threshold, failing-over only the particular memory block;

whereby accesses to non-failed-over memory blocks are satisfied by the memory blocks in the memory modules.

24. The method of claim 23 further comprising the steps of:

detecting an access to a failed-over memory block; and

satisfying the access to the failed-over memory block from an auxiliary memory block.

25. The method of claim 23 further comprising the step of performing a tag look-up to determine whether a memory block access is to a failed-over memory block.

26. The method of claim 25, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising the step of confirming that digital information stored in the corresponding auxiliary memory block to the looked-up tag is valid.

27. The method of claim 25, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising the step of sending a hit signal indicating that the access to the failed-over memory block will be satisfied by the corresponding auxiliary memory block.

28. The method of claim 25, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising the step of accessing the corresponding auxiliary memory block indicated by the looked-up tag.

29. The method of claim 25, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising the step of satisfying the access to the failed-over memory block from the corresponding auxiliary memory block.

30. The method of claim 23 further comprising the step of storing a tag value corresponding to the failed-over memory block.

31. The method of claim 30 further comprising the step of transferring digital information from the failed-over memory block to the auxiliary memory block.

32. The method of claim 31 further comprising the step of correlating the tag value with an auxiliary memory block.

33. The method of claim 30 further comprising the step of setting a valid flag for the tag value.

34. The method of claim 23 further comprising the step of transferring digital information stored in the failed-over memory block to an auxiliary memory location.