Processing unit and method of debugging the processing unit

• US 6,505,309 B1
• Filed: 03/19/1999
• Issued: 01/07/2003
• Est. Priority Date: 09/21/1998
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Nagano, Yasushi, Okabayashi, Toru
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/272,401
• Time in Patent Office: 1,390 Days
• Field of Search: 714/35, 714/34, 714/38, 714/726, 714/30, 714/47, 714/25, 714/40, 714/744, 714/736, 714/733, 712/227, 711/113, 711/118, 711/123, 711/130, 711/135, 711/138
• US Class Current: 714/35
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A processing unit has an operation unit and a cache memory, and further has a debug support unit and a non-cache control circuit. The debug support unit outputs a debug mode signal when an address of a program being currently executed and an optional address set for debugging coincide with each other, and the non-cache control circuit controls the operation of the cache memory via the debug mode signal and outputs the debug mode signal externally of the processing unit.

Claims

1. A processing unit having an operation unit, comprising:

a cache memory that holds a data when the cache memory is deactivated and allows the use of the data when the cache memory is not deactivated;

a debug support unit that outputs a debug mode signal when an address of a command being executed coincides with an address set for debugging; and

a non-cache control circuit that controls the operation of the cache memory via the debug mode signal, wherein the non-cache control circuit deactivates the cache memory when receiving the debug mode signal and does not deactivate the cache memory when not receiving the debug mode signal.

2. A processing unit as claimed in claim 1, wherein said debug .mode signal is defined at the same timing as that at which an address signal is changed or at a timing prior thereto.

3. A processing unit as claimed in claim 2, wherein when an external address is used by said processing unit, said debug mode signal is involved in determining the external address when it is determined, whereby a user area and a debugger area of an external memory are separated from each other.

4. A processing unit as claimed in claim 2, further comprising a bus interface unit having a decoding circuit, wherein when said decoding circuit decodes an address signal inside said processing unit, said decoding circuit executes a decoding with said debug mode signal being involved when said debug mode signal is asserted and generates a chip select signal for selection of a width for an external bus.

5. A processing unit as claimed in claim 2, further comprising a memory management unit having an address converting circuit and a selector, wherein:

said address converting circuit converts a logical address from said operation unit for supply to said selector; and

said selector is adapted to select the logical address from said operation unit and the address converted by said address converting circuit with said debug mode signal for output, wherein when said selector decodes said address signal inside said processing unit, said selector selects the logical address from said operation unit and outputs the same as it is to thereby dispose a debug routine on the same address.

6. A processing unit as claimed in claim 5, further comprising a main memory that is managed by said memory management unit.

15. A processing unit as claimed in claim 1, wherein said non-cache control circuit deactivates said cache memory so as to make it hold data in said debugging mode, whereby the data so held in said cache memory is used as they are when said debugging mode is switched to a normal mode.

7. A method of debugging a processing unit having an operation unit and a cache memory, comprising the steps of:

activating a debug mode and outputting a debug mode signal from a debug support unit when an address set for debugging and an address of a command being currently executed coincide with each other; and

deactivating the cache memory such that the cache memory holds therein data regardless of activation of the debug mode, whereby the data in the cache memory is used in a normal mode associated with other commands.

8. A method of debugging a processing unit as claimed in claim 7, wherein said debug mode signal is defined at the same timing as that at which an address signal is changed or at a timing prior thereto.

9. A method of debugging a processing unit as claimed in claim 8, wherein when said address signal is decoded externally of said processing unit, said debug mode signal is involved in the decoding when it is asserted, whereby a user area and a debugger area of an external unit are separated from each other.

10. A method of debugging a processing unit as claimed in claim 8, wherein when said address signal is decoded internally of said processing unit, said debug mode signal is involved in the decoding when it is asserted, whereby a chip select signal is generated for selection of a width for an external bus.

11. A method of debugging a processing unit as claimed in claim 8, wherein when said address signal is decoded internally by said processing unit, said address signal is separated from those whose addresses are to be converted using said debug mode signal so that the debug routine can be disposed at the same address.

12. A processing unit having a cache memory, comprising:

a debug support section that outputs a debug mode signal when an address of a command being executed coincides with a predefined debugging address; and

a non-cache control section that controls the operation of the cache memory according to the debug mode signal, wherein the non-cache control section deactivates the cache memory for the command with the predefined debugging address, and allows the cache memory to operate normally for other commands that coincide with other addresses.

13. The processing unit as claimed in claim 12, further comprising:

a memory management unit that converts addresses based upon a selection, wherein the memory management unit converts a logical address to the predefined debugging address when the selection is debug.

14. The processing unit as claimed in claim 13, further comprising:

a main memory, separate from the processing unit, that stores the program, debug information and a results of the program, wherein the main memory stores the program, debug information and the results of the program in the predefined debugging address and stores other information in a second area.