Vertical double gate transistor structure

• US 6,506,638 B1
• Filed: 10/12/2000
• Issued: 01/14/2003
• Est. Priority Date: 10/12/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/689,063
• Time in Patent Office: 824 Days
• Field of Search: 257/302, 257/329, 257/401, 438/156, 438/157, 438/212
• US Class Current: 438/156
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bonding technique can be utilized to form the substrate.

Claims

1. A method of manufacturing a vertical transistor, the method comprising:

providing a semiconductor substrate including a semiconductor base layer below a first insulative layer, the first insulative layer being below a first semiconductor layer, and the first semiconductor layer being below a second insulative layer;

providing an aperture through the first insulative layer, the first semiconductor layer, and the second insulative layer;

doping the semiconductor substrate through the aperture; and

providing an amorphous semiconductor layer above the second insulative layer and within the aperture.

2. The method of claim 1, further comprising:

doping the amorphous semiconductor layer.

3. The method of claim 2, further comprising annealing the amorphous semiconductor layer.

4. The method of claim 3, further comprising etching the amorphous semiconductor layer before the annealing step.

5. The method of claim 4, wherein the amorphous semiconductor layer is etched to have a width between 500-2000Å

.

6. The method of claim 1, further comprising:

before the providing an amorphous semiconductor layer step, providing dielectric spacers on side walls of the aperture.

7. The method of claim 6, wherein the dielectric spacers are silicon nitride.

8. The method of claim 1, wherein the aperture divides the first semiconductor layer into a first portion including a first gate conductor on a first side of the aperture and a second portion including a second gate conductor on the other side of the aperture.

9. The method of claim 1, wherein the semiconductor substrate includes single crystalline silicon.

10. The method of claim 1, wherein a channel region is located between the first insulative layer and the second insulative layer in the aperture.

11. A vertical transistor, comprising:

a first gate conductor disposed above a top surface of a substrate;

a second gate conductor disposed above the top surface of the substrate, wherein the first gate conductor is located between two dielectric layers, wherein the second gate conductor is located between two dielectric layers;

a source disposed at least below partially above the top surface of the substrate;

a drain disposed entirely above the top surface of the substrate; and

a channel region between the first gate conductor and the second gate conductor and between the drain and the source, the channel region being at least partially above the top surface of the substrate, wherein a first spacer is silicon nitride provided on a side wall of the first gate conductor, and wherein the channel region is a 90-280 Å

wide.

12. The transistor of claim 11, wherein the channel region is 90-280 Å

wide.

13. The transistor of claim 11, wherein the channel region is 500-1000 Å

long.

14. The transistor of claim 12, wherein the channel region is 90-280 Å

wide.

15. A vertical transistor, comprising:

a first gate conductor disposed above a top surface of a substrate;

a second gate conductor disposed above the top surface of the substrate, wherein the first gate conductor is located between two dielectric layers, wherein the second gate conductor is located between two dielectric layers;

a source disposed at least below partially above the top surface of the substrate;

a drain disposed entirely above the top surface of the substrate; and

a channel region between the first gate conductor and the second gate conductor and between the drain and the source, the channel region being at least partially above the top surface of the substrate, wherein a first spacer is disposed between the channel region and the first gate conductor and a second spacer is disposed between the channel region and the second gate conductor, wherein the channel region is 500-1000 Å

long.

16. A vertical transistor, comprising:

a first gate conductor disposed above a top surface of a substrate;

a second gate conductor disposed above the top surface of the substrate, wherein the first gate conductor is located between a first pair of dielectric layers, wherein the second gate conductor is located between a second pair of dielectric layers;

a source disposed at least below partially above the top surface of a the substrate;

a drain disposed entirely above the top surface of the substrate; and

a channel region between the first gate conductor and the second gate conductor and between the drain and the source, the channel region being at least partially above the top surface of the substrate, wherein a first spacer is disposed between the channel region and the first gate conductor and a second spacer is disposed between the channel region and the second gate conductor, wherein the dielectric layers of the first pair and the second pair are each 50-250 Å

thick.

17. A process of forming a vertical transistor having a channel region at least partially above a top surface of a substrate, the process comprising:

providing a first dielectric layer, a silicon layer and second dielectric layer above a top surface of the substrate;

providing an aperture in the first dielectric layer, the silicon layer and the second dielectric layer;

doping the substrate through the aperture;

forming a semiconductor layer above the second dielectric layer and within the aperture;

doping the semiconductor layer; and

annealing the semiconductor layer.

18. The process of claim 17, wherein the silicon layer includes a first portion being a first gate conductor and a second portion being a second gate conductor.

19. The process of claim 18,

wherein the aperture is 90-280 Å wide.

20. The process of claim 19, wherein the semiconductor layer includes amorphous silicon.

21. A process of forming a vertical transistor having a channel region at least partially above a top surface of a substrate, the process comprising steps of;

a) providing a first dielectric layer, a first semiconductor layer and a second dielectric layer above a top surface of the substrate;

b) providing an aperture in the first dielectric layer, the first semiconductor layer and the second dielectric layer, the aperture reaching the substrate at a location;

c) providing a doped region located at the location;

d) forming a second semiconductor layer above the second dielectric layer and within the aperture;

e) doping the second semiconductor layer; and

f) annealing the second semiconductor layer, wherein step (b) is performed before step (c).

22. A vertical transistor, comprising;

a first doped source/drain region in a substrate;

a channel region disposed above the first doped source/drain region, the channel region having a bottom above the first doped source/drain region, a first side, and a second side, the channel region being 90-280 Å

wide and 500-100 Å

long;

a first gate conductor isolated from the substrate and above the a substrate, the first gate conductor being adjacent a first dielectric structure including silicon nitride on the first side of the channel region;

a second gate conductor isolated from the substrate and above the substrate, the second gate conductor being adjacent a second dielectric structure including silicon nitride on the second side of the channel region; and

a second source/drain region disposed entirely above the substrate and disposed above the channel region and the first gate conductor and the second gate conductor.