Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile
First Claim
1. A method of controlling junction contour within a MOSFET device, comprising:
- forming insulating material into a contoured L-shaped spacer adjacent a gate stack; and
implanting a source-drain junction through the contoured L-shaped spacer to create a stepped junction contour and extended source-drain channel wherein the contoured L-shaped spacer is formed from an L-shaped spacer which is contoured to include reduced-height cutouts proximal the gate stack to control implantation profiling.
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Abstract
A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.
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Citations
16 Claims
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1. A method of controlling junction contour within a MOSFET device, comprising:
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forming insulating material into a contoured L-shaped spacer adjacent a gate stack; and
implanting a source-drain junction through the contoured L-shaped spacer to create a stepped junction contour and extended source-drain channel wherein the contoured L-shaped spacer is formed from an L-shaped spacer which is contoured to include reduced-height cutouts proximal the gate stack to control implantation profiling. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a MOSFET device with a controlled junction profile and a gate stack having a base and a top on a silicon substrate, comprising:
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shallow amorphization implanting within the substrate after formation of the gate stack;
depositing a first spacer layer and a second spacer layer;
forming a third spacer at the base of the gate stacks;
removing portions of the first and the second spacer which are not covered by the third spacer to form said first spacer and said second spacer into L-shaped first and second spacers;
removing the third spacer and a portion of the first spacer positioned adjacent the gate stack;
deep amorphization implanting of dopants through said first and second L-shaped spacers, in such a manner that;
the depth of implantation is responsive to the geometry of said first and second L-shaped spacers;
surface annealing to recrystallize the silicon substrate and to activate the dopants to form source and drain regions in said silicon substrate; and
forming silicide on the source, drain, and gate regions, whereupon conventional fabrication steps may be utilized to provide electrical connections and complete MOSFET device fabrication. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification