Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile

• US 6,506,650 B1
• Filed: 04/27/2001
• Issued: 01/14/2003
• Est. Priority Date: 04/27/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/843,782
• Time in Patent Office: 627 Days
• Field of Search: 438/231, 438/230, 438/595, 438/649, 438/651, 438/655, 438/682, 438/305, 438/528, 438/592, 438/301
• US Class Current: 438/301
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer

Abstract

A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.

Claims

1. A method of controlling junction contour within a MOSFET device, comprising:

forming insulating material into a contoured L-shaped spacer adjacent a gate stack; and

implanting a source-drain junction through the contoured L-shaped spacer to create a stepped junction contour and extended source-drain channel wherein the contoured L-shaped spacer is formed from an L-shaped spacer which is contoured to include reduced-height cutouts proximal the gate stack to control implantation profiling.

2. A method as recited in claim 1, wherein forming the contoured L-shaped spacer comprises depositing layers of insulation followed by selective etching thereof.

3. A method as recited in claim 2, wherein the deposited layers comprise a first layer and a second layer of insulating material.

4. A method as recited in claim 3, wherein selective etching of the first layer and second layer is controlled by first forming a third spacer adjacent the gate stack to prevent portions of the first and second layer, adjacent the gate stack, from being etched.

5. A method as recited in claim 3, wherein the first layer of insulating material comprises a liner oxide material.

6. A method as recited in claim 3, wherein the second layer of insulating material comprises a nitride material.

7. A method of fabricating a MOSFET device with a controlled junction profile and a gate stack having a base and a top on a silicon substrate, comprising:

shallow amorphization implanting within the substrate after formation of the gate stack;

depositing a first spacer layer and a second spacer layer;

forming a third spacer at the base of the gate stacks;

removing portions of the first and the second spacer which are not covered by the third spacer to form said first spacer and said second spacer into L-shaped first and second spacers;

removing the third spacer and a portion of the first spacer positioned adjacent the gate stack;

deep amorphization implanting of dopants through said first and second L-shaped spacers, in such a manner that;

the depth of implantation is responsive to the geometry of said first and second L-shaped spacers;

surface annealing to recrystallize the silicon substrate and to activate the dopants to form source and drain regions in said silicon substrate; and

forming silicide on the source, drain, and gate regions, whereupon conventional fabrication steps may be utilized to provide electrical connections and complete MOSFET device fabrication.

8. A method as recited in claim 7, wherein the first spacer layer is deposited to a depth of between 100 Angstroms to 200 Angstroms.

9. A method as recited in claim 7, wherein the second spacer layer is deposited to a depth of between 250 Angstroms to 400 Angstroms.

10. A method as recited in claim 7, wherein the third spacer comprises an oxide material.

11. A method as recited in claim 7, wherein forming of the third spacer comprises depositing an insulating material followed by selective etching to remove portions of the third spacer not adjacent the gate stack.

12. A method as recited in claim 11, wherein the material of the third spacer is deposited to a depth of between 500 Angstroms and 1000 Angstroms.

13. A method as recited in claim 11, wherein the selective etching of the third spacer is performed comprising a time-controlled wet etching process.

14. A method as recited in claim 7, wherein deep amorphization implanting is performed to create a depth at the junction of between 30 nanometers to 40 nanometers and under the source-drain regions of between 60 nanometers to 100 nanometers.

15. A method as recited in claim 7, wherein surface annealing is performed at a temperature range of from 500°

C. to 600°

C.

16. A method as recited in claim 7, wherein silicide is formed to a depth which exceeds the junction depth implanted beneath the gate electrode.