Power transistors for radio frequencies

• US 6,507,047 B2
• Filed: 05/17/2001
• Issued: 01/14/2003
• Est. Priority Date: 05/17/2000
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Litwin, Andrej
• Primary Examiner(s): Eckert, II, George C.
• Application Number:
  US09/858,902
• Publication Number:
  US 20020014670A1
• Time in Patent Office: 607 Days
• Field of Search: 257/77, 257/341, 257/343, 257/401, 257/728, 438/176, 438/167
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 μm. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 μm. The distances from the long sides of the rectangular area to the edges of the chip should be at least 50% and preferably 60% of the thickness of the chip to allow a good thermal flow out of the active rectangular area. A plurality of such very elongated active areas can be located on a single chip.

Claims

1. A transistor on a SiC-substrate in a chip, comprising:

a plurality of densely-stacked transistor cells arranged in parallel, each transistor cell comprising parallel, strip-shaped regions forming electrodes and active areas of the transistor cell, and each transistor cell having neighboring transistor cells sharing drain and source electrodes with the neighboring transistor cells, the transistor cells occupying a rectangular area on the SiC-substrate.

wherein the rectangular area is elongated having a width not larger than substantially 50 μ

m.

2. The transistor of claim 1, wherein in said rectangular area, the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area, so that the strip-shaped regions will have a length not larger than substantially 50 μ

m.

3. The transistor of claim 1, wherein the distances from the long sides of the rectangular area to edges of the chip area at least 50% of the thickness of chip.

4. The transistor of claim 1, wherein the distances from the long sides of the rectangular area to edges of the chip are least 60% of the thickness of the chip.

5. The transistor of claim 1, wherein a plurality of separate rectangular areas are arranged, the rectangular areas having long sides parallel to each other and being placed at a uniform distance of each other, the rectangular areas separated by areas having a width corresponding to at least twice the shortest distances from the long sides of the rectangular areas to edges of the chip.

6. The transition of claim 1, wherein an operating frequency of the transistor is in the range of several hundred MHz up to and into the microwave region.

7. The transistor of claim 1, wherein an operating frequency of the transistor is in the range of several hundred MHz up to 45 GHz.

8. The transistor of claim 1, wherein the width of the rectangular area is independent of an operating frequency of the transistor.

9. The transistor of claim 1, wherein the width of the rectangular area at 50 μ

m or less is set to substantially reduce or minimize a surface temperature of the transistor under operating conditions.