Multiple layer phase-change memory

• US 6,507,061 B1
• Filed: 08/31/2001
• Issued: 01/14/2003
• Est. Priority Date: 08/31/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Lowrey, Tyler A., Hudgens, Stephen J., Klersy, Patrick J.
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/945,331
• Time in Patent Office: 501 Days
• Field of Search: 257/296, 257/295, 257/309, 257/310, 257/19, 257/28, 257/52
• US Class Current: 257/295
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/861 Thermal details
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Claims

1. A memory cell comprising:

a first layer of a phase-change material;

a second layer of a phase-change material; and

a non-phase-change material between said first and second layers, said non-phase-change material completely separating said first layer from said second layer.

2. The cell of claim 1 wherein said first layer of a phase-change material is made of a chalcogenide material.

3. The cell of claim 1 wherein said first and second layers are different phase-change materials.

4. The cell of claim 1 wherein said first and second layers of phase-change material are the same material.

5. The cell of claim 1 wherein said non-phase-change material is a conductor.

6. The cell of claim 1 including a semiconductor substrate and an electrical contact formed in said substrate.

7. The cell of claim 6 including an insulating layer formed over said substrate, and a passage formed through said insulating layer.

8. The cell of claim 7 wherein said first and second layers are formed at least in part in said passage.

9. The cell of claim 8 including a sidewall spacer formed in said passage over said contact.

10. The cell of claim 1 wherein said first and second layers are cup-shaped.

11. The cell of claim 1 wherein said second layer of phase-change material is configured to provide thermal isolation.

12. A memory cell comprising:

a first layer of a phase-change material; and

a second layer of a phase-change material, only one of said first and second layers of phase-change material being programmable.

13. The cell of claim 12 including a non-phase-change material between said first and second layers.

14. The cell of claim 13 wherein said non-phase-change material is a conductor.

15. The cell of claim 12 wherein the first layer of phase-change material is programmable and the second layer of phase-change material acts as an insulator for said first layer of phase-change material.

16. The cell of claim of 12 wherein said first layer of phase-change material is made of a chalcogenide material.

17. The cell of claim 12 wherein said first and second layers are different phase-change materials.

18. The cell of claim 12 wherein said first and second layers of phase-change material are the same material.

19. The cell of claim 12 including a semiconductor substrate and an electrical contact formed in said substrate.

20. The cell of claim 19 including an insulating layer formed over said substrate, and a passage formed through said insulating layer.

21. The cell of claim 20 wherein said first and second layers are formed at least in part in said passage.

22. A memory cell comprising:

a first layer of a phase-change material;

a second layer of a phase-change material different from the phase-change material of said first layer; and

a non-phase-change material between said first and second layers.

23. The cell of claim 22 wherein said non-phase-change material is an electrical conductor.

24. The cell of claim 22 wherein said second layer of phase-change material is configured to provide thermal isolation.

25. A memory cell comprising:

a first layer of a phase-change material;

a second layer of a phase-change material; and

a conductive non-phase-change material between said first and second layers.

26. The cell of claim 25 wherein said first and second layers are different phase-change materials.

27. The cell of claim 25 wherein said first and second layers are of the same material.