Semiconductor device and method of making

• US 6,507,070 B1
• Filed: 11/25/1996
• Issued: 01/14/2003
• Est. Priority Date: 11/25/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Robb, Stephen P., Shen, Zheng, Mitter, Chang Su
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US08/755,926
• Time in Patent Office: 2,241 Days
• Field of Search: 257/146, 257/147, 257/148, 257/149, 257/150, 257/151, 257/156, 257/157, 257/344, 257/341, 257/139, 257/263
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device (10) is formed that is bi-lateral and has a voltage blocking capability that is well suited to applications involving portable electronics. The semiconductor device has an epitaxial layer (14) that is formed on a semiconductor substrate (11). A doped region (24) is formed that extends from a top surface (16) of the epitaxial layer (14) to the underlying semiconductor substrate (11). The semiconductor device (10) has a source region (31) that is separated from the doped region (24) to provide a channel region (29). The channel region (29) is modulated by a gate structure (20) to determine if a current flow should be allowed through semiconductor device (10) or if semiconductor device (10) is to provide voltage blocking capability.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate has a top surface and a bottom surface;

an epitaxial layer of a second conductivity type overlying the top surface of the semiconductor substrate and having a top surface;

a first doped region in the epitaxial layer, wherein the first doped region is doped to the first conductivity type and contacts the semiconductor substrate, and wherein the first doped region is electrically isolated from the epitaxial layer by a PN junction;

a second doped region in the epitaxial layer, wherein the second doped region is doped to the first conductivity type, extends from the top surface of the epitaxial layer, and overlaps at least a portion of the first doped region, and wherein the second doped region is electrically isolated from the epitaxial layer by a PN junction;

a third doped region in the epitaxial layer, wherein the second doped region and the third doped region comprise titanium, wherein the third doped region is doped to the first conductivity type and extends from the top surface of the epitaxial layer, wherein the third doped region is electrically isolated from the epitaxial layer by a PN junction and is separated from the second doped region by a first distance to provide a channel region, wherein the channel region is electrically floating such that the channel region prevents the flow of current between the first doped region and the third doped region if the third doped region is at a voltage potential that is at least 30 volts higher than the first doped region, and the channel region prevents the flow of current between the first doped region and the third doped region if the first doped region is at a voltage potential that is at least 30 volts higher than the third doped region; and

a gate structure overlying at least a portion of the channel region and at least a portion of the second doped region.