Cu-balanced substrate
First Claim
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1. A substrate for attaching a semiconductor die to a printed circuit board, the substrate comprising:
- an upper surface containing electrically functional metal lines; and
a lower surface containing electrically functional metal lines;
wherein, at least one of the upper and lower surfaces further contains an electrically non-functional metal area for improved strength and rigidity and reduced warpage and bending.
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Abstract
A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.
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Citations
15 Claims
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1. A substrate for attaching a semiconductor die to a printed circuit board, the substrate comprising:
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an upper surface containing electrically functional metal lines; and
a lower surface containing electrically functional metal lines;
wherein, at least one of the upper and lower surfaces further contains an electrically non-functional metal area for improved strength and rigidity and reduced warpage and bending.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
the vais electrically connect the Cu or Cu alloy functional lines on the upper and lower surfaces; and
the lower surface of the substrate comprises solder balls affixed thereto.
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10. A circuit assembly comprising:
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the substrate according to claim 9;
at least one semiconductor die attached to the upper surface of the substrate;
a printed circuit board attached to the lower surface of the substrate; and
bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.
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11. A circuit assembly comprising:
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the substrate according to claim 5;
at least one semiconductor die attached to the upper surface of the substrate;
a printed circuit board attached to the lower surface of the substrate; and
bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.
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12. The substrate according to claim 3, comprising vias extending through the substrate between the upper and lower surfaces, wherein the vias are offset from one another such that less than 20% of the vias are aligned.
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13. The substrate according to claim 12, comprising at least 48 vias.
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14. The substrate according to claim 12, wherein:
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the vias electrically connect functional Cu or Cu alloy lines on the upper and lower surfaces; and
the lower surface of the substrate comprises solder balls affixed thereto.
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15. A circuit assembly comprising:
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the substrate according to claim 14;
at least one semiconductor die attached to the upper surface of the substrate;
a printed circuit board attached to the lower surface of the substrate; and
bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.
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Specification