Cu-balanced substrate

• US 6,507,100 B1
• Filed: 01/31/2001
• Issued: 01/14/2003
• Est. Priority Date: 06/28/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Valluri, Viswanath, Fontecha, Edwin, Lee, Melissa Siow-Lui
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Dao H.
• Application Number:
  US09/772,888
• Time in Patent Office: 713 Days
• Field of Search: 257/691, 257/693, 257/696, 257/697, 257/701, 257/735, 257/737, 257/773, 361/380, 361/396, 361/762, 361/766, 367/760, 367/771, 367/808, 174/52.4, 174/262
• US Class Current: 257/697
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.

Claims

1. A substrate for attaching a semiconductor die to a printed circuit board, the substrate comprising:

an upper surface containing electrically functional metal lines; and

a lower surface containing electrically functional metal lines;

wherein, at least one of the upper and lower surfaces further contains an electrically non-functional metal area for improved strength and rigidity and reduced warpage and bending.

2. The substrate according to claim 1, wherein the metal for the functional lines and the metal for the electrically non-functional area comprises copper (Cu) or a Cu alloy.

3. The substrate according to claim 2, wherein each of the upper surface and the lower surface contains at least one electrically non-functional area of Cu or a Cu alloy.

4. The substrate according to claim 3, wherein the at least one electrically non-functional area is in the form of a grid.

5. The substrate according to claim 3, wherein the ratio of the total area of electrically functional lines and electrically non-functional area or areas on one of the upper surface or the lower surface is about 55% to about 100% of the total area of electrically functional lines and electrically non-functional area or areas on the other of the lower surface or the upper surface.

6. The substrate according to claim 5, wherein the ratio is about 60% to about 80%.

7. The substrate according to claim 5, comprising vias extending through the substrate between the upper and lower surfaces, wherein the vias are offset from one another such that less than 20% of the vias are aligned.

8. The substrate according to claim 7, comprising at least 48 vias.

9. The substrate according to claim 7, wherein:

the vais electrically connect the Cu or Cu alloy functional lines on the upper and lower surfaces; and

the lower surface of the substrate comprises solder balls affixed thereto.

10. A circuit assembly comprising:

the substrate according to claim 9;

at least one semiconductor die attached to the upper surface of the substrate;

a printed circuit board attached to the lower surface of the substrate; and

bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.

11. A circuit assembly comprising:

the substrate according to claim 5;

at least one semiconductor die attached to the upper surface of the substrate;

a printed circuit board attached to the lower surface of the substrate; and

bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.

12. The substrate according to claim 3, comprising vias extending through the substrate between the upper and lower surfaces, wherein the vias are offset from one another such that less than 20% of the vias are aligned.

13. The substrate according to claim 12, comprising at least 48 vias.

14. The substrate according to claim 12, wherein:

the vias electrically connect functional Cu or Cu alloy lines on the upper and lower surfaces; and

the lower surface of the substrate comprises solder balls affixed thereto.

15. A circuit assembly comprising:

the substrate according to claim 14;

at least one semiconductor die attached to the upper surface of the substrate;

a printed circuit board attached to the lower surface of the substrate; and

bond wires electrically connecting bond pads on the at least one semiconductor die to the substrate.