Digital configurable macro architecture

• US 6,507,214 B1
• Filed: 07/18/2001
• Issued: 01/14/2003
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/909,045
• Time in Patent Office: 545 Days
• Field of Search: 326/38-41
• US Class Current: 326/38
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Claims

1. A programmable digital device comprising:

a first programmable digital circuit block which is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein said first programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein said first programmable digital circuit block includes;

a first configuration register for receiving and storing a plurality of configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said first configuration register configures said first programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data; and

a first plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said first programmable digital circuit block, wherein said first configuration register configures and selects any of said first plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data.

2. The programmable digital device as recited in claim 1 further comprising:

a second programmable digital circuit block which is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein said second programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein said second programmable digital circuit block includes;

a second configuration register for receiving and storing a plurality of second configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said second configuration register configures said second programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said second configuration data; and

a second plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said second programmable digital circuit block, wherein said second configuration register configures and selects any of said second plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said second configuration data.

3. The programmable digital device as recited in claim 2 wherein said first and second programmable digital circuit blocks are selectively configurable to couple to one another in series.

4. The programmable digital device as recited in claim 2 wherein said first and second programmable digital circuit blocks are selectively configurable to couple to one another in parallel.

5. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

6. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

7. The programmable digital device as recited in claim 1 wherein said predetermined digital functions are 8-bit predetermined digital functions.

8. A programmable digital device comprising:

an array of programmable digital circuit blocks, each programmable digital circuit block is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein each programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein each programmable digital circuit block includes;

a configuration register for receiving and storing a plurality of configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said configuration register configures said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data; and

a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data.

9. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is selectively configurable to couple to another programmable digital circuit block in series.

10. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is selectively configurable to couple to another programmable digital circuit block in parallel.

11. The programmable digital device as recited in claim 8 wherein said array includes a first group of programmable digital circuit blocks and a second group of programmable digital circuit blocks.

12. The programmable digital device as recited in claim 11 wherein said first group of programmable digital circuit blocks are configurable to perform any one of a first plurality of predetermined digital functions, wherein said first plurality of predetermined digital functions includes a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

13. The programmable digital device as recited in claim 11 wherein said second group of programmable digital circuit blocks are configurable to perform any one of a second plurality of predetermined digital functions, wherein said second plurality of predetermined digital functions includes a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

14. The programmable digital device as recited in claim 8 wherein said predetermined digital functions are 8-bit predetermined digital functions.

15. A controller apparatus comprising:

a first programmable digital circuit block which is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein said first programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein said first programmable digital circuit block includes;

a first configuration register for receiving and storing a plurality of configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said first configuration register configures said first programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data; and

a first plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said first programmable digital circuit block, wherein said first configuration register configures and selects any of said first plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data.

16. The controller apparatus as recited in claim 15 further comprising:

a second programmable digital circuit block which is selectably configurable to perform any one of a plurality of predetermined digital functions, wherein said second programmable digital circuit block is dynamically configurable from any one of said predetermined digital functions to any one of said predetermined digital functions, wherein said second programmable digital circuit block includes;

a second configuration register for receiving and storing a plurality of second configuration data corresponding to any one of said plurality of predetermined digital functions, wherein said second configuration register configures said second programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said second configuration data; and

a second plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said second programmable digital circuit block, wherein said second configuration register configures and selects any of said second plurality of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said second configuration data.

17. The controller apparatus as recited in claim 16 wherein said first and second programmable digital circuit blocks are selectively configurable to couple to one another in series.

18. The controller apparatus as recited in claim 16 wherein said first and second programmable digital circuit blocks are selectively configurable to couple to one another in parallel.

19. The controller apparatus as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

20. The controller apparatus as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

21. The controller apparatus as recited in claim 15 wherein said predetermined digital functions are 8-bit predetermined digital functions.