Power device driving circuit and associated methods

• US 6,507,226 B2
• Filed: 07/25/2001
• Issued: 01/14/2003
• Est. Priority Date: 07/31/2000
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Doyle, Brent R., Swonger, James W.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/915,119
• Publication Number:
  US 20020014900A1
• Time in Patent Office: 538 Days
• Field of Search: 327/333, 327/108, 327/112, 327/434, 327/435, 327/563, 327/544, 326/80, 326/81, 326/82, 326/83
• US Class Current: 327/108
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Claims

1. A circuit for driving a power device comprising:

a low side gate driver; and

a high side gate driver adjacent the low side gate driver and comprising

a high side gate driver logic input,

a high side gate driver output,

a latch connected between the high side gate driver logic input and the high side gate driver output, and

a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

2. A circuit according to claim 1 wherein the high side gate driver further comprises first and second level shifting signal paths connecting the high side gate driver logic input and inputs of the latch.

3. A circuit according to claim 2 wherein the control circuit comprises:

a first switch in the first level shifting path between the high side gate driver logic input and a first input of the latch controlled by the output of the latch; and

a second switch in the second level shifting path between the high side gate driver logic input and a second input of the latch controlled by an inverted output of the latch.

4. A circuit according to claim 3 wherein the first and second switches comprise P-channel pass transistors.

5. A circuit according to claim 2 wherein the high side gate driver further comprises:

a high side floating voltage supply; and

respective loads connecting the first and second level shifting signal paths to the high side floating voltage supply.

6. A circuit according to claim 5 wherein the respective loads comprise:

a first resistor connecting the first level shifting signal path to the high side floating voltage supply; and

a second resistor connecting the second level shifting signal path to the high side floating voltage supply.

7. A circuit according to claim 2 wherein the high side gate driver further comprises:

a first current source in the first level shifting path controlled by the high side gate driver logic input; and

a second current source, out of phase with the first current source, in the second level shifting path controlled by the high side gate driver logic input.

8. A circuit according to claim 7 wherein the first and second current sources comprise respective out of phase NMOS pass transistors controlled by the high side gate driver logic input and connected to a reference voltage supply.

9. A circuit according to claim 1 wherein the latch comprises an active low SR latch.

10. A high side gate driver for a power device driving circuit, the high side gate driver comprising:

a latch for receiving a high side gate driver logic input signal and outputting a high side gate driver output signal; and

a control circuit for receiving the high side gate driver output signal of the latch and for controlling signals to the latch based upon the high side gate driver output signal.

11. A high side gate driver according to claim 10 further comprising first and second level shifting signal paths for conducting the high side gate driver logic input signal to inputs of the latch.

12. A high side gate driver according to claim 11 wherein the control circuit comprises:

a first switch in the first level shifting path controlled by the high side gate driver output signal; and

a second switch in the second level shifting path controlled by an inverted high side gate driver output signal.

13. A high side gate driver according to claim 12 wherein the first and second switches comprise P-channel pass transistors.

14. A high side gate driver according to claim 11 further comprising respective loads connecting the first and second level shifting signal paths to a high side floating supply voltage.

15. A high side gate driver according to claim 14 wherein the respective loads comprise:

a first resistor connecting the first level shifting signal path to the high side floating supply voltage; and

a second resistor connecting the second level shifting signal path to the high side floating supply voltage.

16. A high side gate driver according to claim 11 further comprising:

a first current source in the first level shifting path controlled by the high side gate driver logic input signal; and

a second current source, out of phase with the first current source, in the second level shifting path controlled by the high side gate driver logic input signal.

17. A high side gate driver according to claim 16 wherein the first and second current sources comprise respective out of phase NMOS pass transistors controlled by the high side gate driver logic input signal and connected to a reference supply voltage.

18. A high side gate driver according to claim 10 wherein the latch comprises an active low SR latch.

19. A method for driving a power device comprising:

latching a high side gate driver logic input signal with a latch;

outputting a high side gate driver output signal based upon the latched high side gate driver logic input signal; and

controlling the high side gate driver logic input signal based upon the high side gate driver output signal to minimize power consumption.

20. A method according to claim 19 wherein controlling the high side gate driver logic input signal comprises controlling first and second level shifting signal paths which connect a high side gate driver logic input and inputs of the latch.

21. A method according to claim 20 wherein controlling first and second level shifting signal paths comprises:

providing a first switch in the first level. shifting path between the high side gate driver logic input and a first input of the latch controlled by an output of the latch; and

providing a second switch in the second level shifting path between the high side gate driver logic input and a second input of the latch controlled by an inverted output of the latch.

22. A method according to claim 21 wherein the first and second switches comprise P-channel pass transistors.

23. A method according to claim 20 wherein controlling first and second level shifting signal paths further comprises connecting respective loads between the first and second level shifting signal paths and a high side floating voltage supply.

24. A method according to claim 23 wherein the respective loads comprise:

a first resistor connecting the first level shifting signal path to the high side floating voltage supply; and

a second resistor connecting the second level shifting signal path to the high side floating voltage supply.

25. A method according to claim 20 wherein controlling first and second level shifting signal paths further comprises:

providing a first current source in the first level shifting path controlled by the high side gate driver logic input; and

providing a second current source, out of phase with the first current source, in the second level shifting path controlled by the high side gate driver logic input.

26. A method according to claim 25 wherein the first and second current sources comprise respective out of phase NMOS pass transistors controlled by the high side gate driver logic input and connected to a reference voltage supply.