Enhanced linearity, low switching perturbation resistor string matrices

• US 6,507,272 B1
• Filed: 07/26/2001
• Issued: 01/14/2003
• Est. Priority Date: 07/26/2001
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Tang, Hao, Nicholson, Richard, Churchill, Simon
• Primary Examiner(s): Easthom, Karl D.
• Application Number:
  US09/915,464
• Publication Number:
  US 20030020594A1
• Time in Patent Office: 537 Days
• Field of Search: 338/295, 338/235, 338/239, 338/203, 338/260, 338/319, 338/320, 341/154
• US Class Current: 338/320
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H03M 1/0648 by arranging the quantisation value generators in a non-sequential pattern layout, e.g. symmetrical
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

Enhanced linearity, low switching perturbation resistor string matrices. The resistor strings are arranged in an array of a plurality of rows of resistive elements and electrically arranged with rows equally spaced above and below the physical centerline of the array being coupled together in an opposite sense. Preferably also physically adjacent rows are equally spaced from the center of the electrical order of rows. This connection prevents accumulation of errors due to vertical and horizontal resistance gradients over the array. Also node selection by controlling node select transistors coupled to column select lines to select one node in each row, and also controlling row select transistors to select the row of the desired node minimizes settling time after a tap change by inducing equal and opposite voltage changes at points close together along the resistor string, whether in the array of the present invention or in the snake configuration.

Claims

1. A resistor string comprising:

a plurality of resistive elements connected in series on a substrate, the plurality of resistive elements being arranged in an array of columns and rows, the array having a physical middle defined by a plurality of rows above and an equal plurality of rows below the physical middle of the array, each pair of rows comprising a row above the physical middle of the array and the row equally spaced below the physical middle of the array being electrically connected together without another row of resistive elements being electrically connected there between to define an electrical order of rows.

2. The resistor string of claim 1 wherein the electrical order is also selected to place physically adjacent rows at positions equally spaced from the center of the electrical order of rows.

3. The resistor string of claim 2 wherein the total number of rows of resistors is 2*N, where N is an even number.

4. The resistor string of claim 2 wherein the total number of rows of resistors is 2*N, where N is an odd number, and wherein the physical center pair of rows is in the center of the electrical order of rows.

5. The resistor string of claim 2 wherein the total number of rows of resistors is 2*N+1, where N is an even number, and wherein the physical center row is in the center of the electrical order of rows.

6. The resistor string of claim 2 wherein the total number of rows of resistors is 2*N+1, where N is an odd number, and wherein the physical center row is in the center of the electrical order of rows.

7. The resistor string of claim 2 wherein the pairs of rows are connected together so that conduction across the array in one row of each of the pairs of rows is in the opposite direction from the conduction across the array in the other row of the respective pair of rows.

8. The resistor string of claim 7 further comprised of a plurality of node select transistors, each having a control terminal controlling the conduction through the respective node select transistor between first and second transistor terminals, each node select transistor having its first terminal coupled to a respective node along the string of resistive elements, the control terminal of the node select transistors in each column all being coupled to a respective column select line, and the second terminal of each node select transistor in each row of the array being coupled to a respective row line.

9. The resistive string of claim 8 further comprised of a row select transistor coupled to each row line.

10. The resistor string of claim 2 wherein the substrate is a silicon substrate.

11. The resistor string of claim 2 wherein the resistive elements are ohmic resistive elements.

12. A resistor string comprising:

a plurality of resistive elements connected in series on a substrate, the plurality of resistive elements being arranged in an array of columns and rows, the array having a physical middle defined by a plurality of rows above and an equal plurality of rows below the physical middle of the array, each pair of rows comprising a row above and a row equally spaced below the physical middle of the array being electrically connected together without another row of resistive elements being electrically connected there between, and connected so that conduction across the array in one row is in the opposite direction from the conduction across the array in the other row of each respective pair of rows; and

,

a plurality of node select transistors, each having a control terminal controlling the conduction through the respective node select transistor between first and second transistor terminals, each node select transistor having its first terminal coupled to a respective node along the resistor string, the control terminal of the node select transistors in each column being coupled to a respective column select line, and the second terminal of each node select transistor in each row of the array being coupled to a respective row line.

13. The resistive string of claim 12 further comprised of a row select transistor coupled to each row line.

14. The resistor string of claim 12 wherein the substrate is a silicon substrate.

15. The resistor string of claim 12 wherein the resistive elements are ohmic resistive elements.

16. The resistor string of claim 12 wherein the electrical order is also selected to place physically adjacent rows at positions equally spaced from the center of the electrical order of rows.

17. The resistor string of claim 16 wherein the total number of rows of resistors is 2*N, where N is an even number.

18. The resistor string of claim 16 wherein the total number of rows of resistors is 2*N, where N is an odd number, and wherein the physical center pair of rows is in the center of the electrical order of rows.

19. The resistor string of claim 16 wherein the total number of rows of resistors is 2*N+1, where N is an even number, and wherein the physical center row is in the center of the electrical order of rows.

20. The resistor string of claim 16 wherein the total number of rows of resistors is 2*N+1, where N is an odd number, and wherein the physical center row is in the center of the electrical order of rows.

21. A method of reducing the effect of resistance gradients in an array of serially connected resistive elements on a substrate comprising:

arranging the plurality of resistive elements in an array of columns and rows, the array having a physical middle defined by a plurality of rows above and an equal plurality of rows below the physical middle of the array; and

,

electrically connecting together each pair of rows comprising a row above the physical middle of the array and the row equally spaced below the physical middle of the array without electrically connecting another row of resistive elements there between.

22. The method of claim 21 further comprising selecting the electrical order to place adjacent physical rows at positions equally spaced from the center of the electrical order of rows.

23. The method of claim 22 wherein the total number of rows of resistors is 2*N, where N is an even number.

24. The method of claim 22 wherein the total number of rows of resistors is 2*N, where N is an odd number, and further comprising selecting the physical center pair of rows to be in the center of the electrical order of rows of resistive elements.

25. The method of claim 22 wherein the total number of rows of resistors is 2*N+1, where N is an even number, and further comprising selecting the physical center row to be in the center of the electrical order of rows of resistive elements.

26. The method of claim 22 wherein the total number of rows of resistors is 2*N+1, where N is an odd number, and further comprising selecting the physical center row to be in the center of the electrical order of rows of resistive elements.

27. The method of claim 22 wherein electrically connecting comprises connecting the pairs of rows together so that conduction across the array in one row of each of the pairs of rows is in the opposite direction from the conduction across the array in the other row of each respective pair of rows.

28. The method of claim 27 further comprised of:

providing a plurality of node select transistors, each having a control terminal controlling the conduction through the node select transistor between first and second transistor terminals;

coupling the first terminal of each node select transistor to a respective node in an array of resistive elements;

coupling the control terminal of the node select transistors in each column to a respective column select line; and

,

coupling the second terminal of each node select transistor in each row of the array to a respective row line.

29. The method of claim 28 further comprised of coupling a row select transistor to each row line.

30. The method of claim 27 wherein the substrate is a silicon substrate.

31. The method of claim 22 wherein the resistors are ohmic resistors.

32. A method of reducing the effect of resistance gradients and switching perturbations in an array of serially connected resistive elements on a substrate comprising:

arranging the plurality of resistive elements in an array of columns and rows, the array having a physical middle defined by a plurality of rows above and an equal plurality of rows below the physical middle of the array; and

,

electrically connecting together each pair of rows comprising a row above and a row equally spaced below the physical middle of the array without electrically connecting another row of resistive elements there between, and connecting the pairs of rows so t hat conduction a cross the array in one row is in the opposite direction from the conduction across the array in the other row of each respective pair of rows;

providing a plurality of node select transistors, each having a control terminal controlling the conduction through the respective node select transistor between first and second transistor terminals;

coupling the first terminal of each node select transistor to a respective node in the array of resistive elements;

coupling the control terminal of the node select transistors in each column a respective column select line; and

,

coupling the second terminal of each node select transistor in each row of the array to a respective row line.

33. The method of claim 32 further comprised of providing a row select transistor coupled to each row line.

34. The method of claim 32 wherein the substrate is a silicon substrate.

35. The method of claim 32 wherein the resistors are ohmic resistors.

36. The method of claim 32 further comprised of selecting the electrical order to place physically adjacent rows at positions equally spaced from the center of the electrical order of rows.

37. The method of claim 36 wherein the total number of rows of resistors is 2*N, where N is an even number.

38. The method of claim 36 wherein the total number of rows of resistors is 2*N, where N is an odd number, and wherein the physical center pair of rows is in the center of the electrical order of rows.

39. The method of claim 36 wherein the total number of rows of resistors is 2*N+1, where N is an even number, and wherein the physical center row is in the center of the electrical order of rows.

40. The method of claim 36 wherein the total number of rows of resistors is 2*N+1, where N is an odd number, and wherein the physical center row is in the center of the electrical order of rows.