Column decoder circuit for page reading of a semiconductor memory

• US 6,507,534 B2
• Filed: 02/27/2001
• Issued: 01/14/2003
• Est. Priority Date: 02/29/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Balluchi, Daniele
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/797,171
• Publication Number:
  US 20010028598A1
• Time in Patent Office: 686 Days
• Field of Search: 365/230.01, 365/230.02, 365/230.03, 365/230.06, 365/231
• US Class Current: 365/230.06
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.

Claims

1. A column decoder circuit for page reading of a semiconductor memory, comprising:

a first level decoder stage having an input connected to an address bus and an output connected to a first level bus;

a second level decoder stage having at input connected to said address bus and connected an output connected to a second level bus; and

a plurality of bit selection stages, each including a plurality of selection branches and a multiplexer, said selection branches being connected to respective inputs of said multiplexer and having a plurality of first level selector stages and a second level selector stage, each of said first level selector stages being connected to said first level bus, to respective bit lines, and to a respective second level selector stage, each second level selector stage having a first addressing circuit for addressing a first group of bit lines;

a second addressing circuit for addressing a second group of bit lines, and

a selection circuit for selecting one of said first and second groups of bit lines.

2. The column decoder circuit of claim 1 wherein one second addressing circuit is within each bit selection stage.

3. The circuit according to claim 1, wherein in each bit selection stage, at least one selection branch comprises a third level selector stage including said selection circuit, said third level selector stage being connected, through a first and a second connection, to a respective on of said second level selector stage, and, through a third connection, to said multiplexer.

4. The circuit according to claim 1, further including a third level decoder stage having an input connected to said address bus and an output connected to said third level selector stage through a third level bus.

5. The circuit according to claim 4, wherein said third level selector stage comprises a current page selector and a next page selector, said current page selector being connected between said first connection and said third connection and having a control terminal connected to said third level bus, said next page selector being connected between said second connection and said third connection and having a control terminal connected to said third level bus.

6. The circuit according to claim 4, wherein said control terminal of said current page selector and said control terminal of said next page selector are connected to distinct lines of said third level bus;

said lines of said third level bus supplying third level signals generated by said third level decoder stage for activating alternatively one of said current page selector and said next page selector.

7. The circuit according to claim 3, wherein in said at least one selection branch, said second level selector stage comprises a plurality of first selectors connected to said first connection and a plurality of second selectors connected to said second connection.

8. The circuit according to claim 7, wherein said at least one selection branch, at least some of said first level selector stages are connected to a respective one of said first selector and to a respective one of said second selector of said second level selector stage.

9. The circuit according to claim 7, wherein said first and second selectors have respective control terminals connected to said first level bus;

at least some of said first selectors having a control terminal connected to the control terminal of a second adjacent selector.

10. The circuit according to claim 7, wherein each bit selection stage comprises a respective standard selection stage having a plurality of further first level selector stages, a standard selector stage and a standard selector;

said standard selector stage comprising a plurality of first selectors which are connected between respective outputs of said further first level selector stages and said standard selector and have respective control terminals connected to said second level bus;

said standard selector being connected to a respective input of said multiplexer and having a control terminal connected to said third level bus.

11. A method for page reading of a semiconductor memory having a first level decoder stage having an input to an address bus and an output connected to a first level bus, a second level decoder stage having an input connected to said address bus and an output connected to a second level bus;

and a plurality of bit selection stages, each bit selection stage comprising a plurality of selection branches and a multiplexer, said selection branches being connected to respective inputs of said multiplexer and having a plurality of first level selector stages and a second level selector stage;

each of said first level selector stages being connected to said first level bus, to respective bit lines, and to a respective second level selector stage;

the method comprising;

addressing a first group of bit lines;

addressing a second group of bit lines, and

selecting one of said first and second groups of bit lines.

12. A memory circuit comprising:

a first level decoder stage having an input connected to an address bus and an output connected to a first level bus;

a second level decoder stage having an input connected to said address bus and an output connected to a second level bus;

a third level decoder stage having an input connect to said address bus and an output connect to a third level bus; and

a plurality of bit selection stages, each including a plurality of selection branches and a multiplexer, said selection branches being connected to respective inputs of said multiplexer and having a plurality of first level selector stages, a plurality of second level selector stages and a plurality of third selector stages, each of said first level selector stages being connected to said first level bus, to respective bit lines, each second level selector stage, being connected to a plurality of outputs of the respective first level selector stage and to the second level bus, and each third level selector stage being connected a plurality of outputs of said respective second level selector stage and to the third level bus, and through an output to said multiplexer.

13. The column decoder circuit of claim 12 wherein one second addressing circuit is within each bit selection stage.

14. The circuit according to claim 12 wherein the third level decoder stage having an input connected to said address bus and an output connected to said third level selector stage through a third level bus.

15. The circuit according to claim 14 wherein said third level selector stage comprises a current page selector and a next page selector, said current page selector being connected between said first connection and said third connection and having a control terminal connected to said third level bus, said next page selector being connected between said second connection and said third connection and having a control terminal connected to said third level bus.

16. The circuit according to claim 14 wherein said control terminal of said current page selector and said control terminal of said next page selector are connected to distinct lines of said third level bus;

said lines of said third level bus supplying third level signals generated by said third level decoder stage for activating alternatively one of said current page selector and said next page selector.

17. The circuit according to claim 13 wherein in said at least one selection branch, said second level selector stage comprises a plurality of first selectors connected to said first connection and a plurality of second selectors connected to said second connection.

18. The circuit according to claim 17 wherein said at least one selection branch, at least some of said first level selector stages are connected to a respective one of said first selector and to a respective one of said second selector of said second level selector stage.

19. The circuit according to claim 17 wherein said first and second selectors have respective control terminals connected to said first level bus;

at least some of said first selectors having a control terminal connected to the control terminal of a second adjacent selector.

20. The circuit according to claim 17 wherein each bit selection stage comprises a respective standard selection stage having a plurality of further first level selector stages, a standard selector stage and a standard selector;

said standard selector stage comprising a plurality of first selectors which are connected between respective outputs of said further first level selector stages and said standard selector and have respective control terminals connected to said second level bus;

said standard selector being connected to a respective input of said multiplexer and having a control terminal connected to said third level bus.

21. A circuit comprising:

a plurality of first decoder circuits each decoder circuit having an input coupled to an address bus and an output coupled to a first bus;

a plurality of first selection circuits, each first selection circuit having a plurality of inputs each input coupled to a bit line, a control input coupled to the first bus and an output;

a second decoder circuit having an input coupled to the address bus and an output coupled to a second bus; and

a plurality of second selection circuit, each second selection circuit having a plurality of inputs such that each input of the second selection circuit is coupled to the output of a first selection circuit of the plurality of first selection circuits, a control input coupled to the second bus and a plurality of outputs each output being a selected bit line coupled to an output data bus.

22. The circuit according to claim 21 further comprising a third decoder circuit having an input coupled to the address bus and an output coupled to a third bus and a plurality of third selection circuits, each third selection circuit having a plurality of inputs coupled to the plurality of outputs of the second selection circuit, a control input coupled to the third bus and an output such that the output provides a selected bit line.

23. The circuit according to claim 22 wherein the plurality of third selection circuits further comprise a current page selector and a next page selector.

24. A column decoder circuit for page reading of a semiconductor memory, comprising:

a first level decoder stage having an input connected to an address bus and an output connected to a first level bus;

a second level decoder stage having an input connected to said address bus and an output connected to a second level bus;

a third level decoder stage having an input connected to said address bus and an output connected to said third level selector stage through a third level bus;

a plurality of bit selection stages, each including a plurality of selection branches and a multiplexer, said selection branches being connected to respective inputs of said multiplexer and having a plurality of first level selector stages and a plurality of second level selector stages each of said first level selector stages being connected to said first level bus, to respective bit lines, and to a respective second level selector stage, each second level selector stage having a first addressing circuit for addressing a first group of bit lines;

a second addressing circuit for addressing a second group of bit lines, and

a selection circuit for selecting one of said first and second groups of bit lines.