Method and apparatus for determining which branch of a network of an integrated circuit has the largest total effective RC delay

• US 6,507,807 B1
• Filed: 08/13/1999
• Issued: 01/14/2003
• Est. Priority Date: 08/13/1999
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: McBride, John G
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/373,682
• Time in Patent Office: 1,250 Days
• Field of Search: 703/14, 703/17, 716/6, 716/16, 716/18, 716/4, 716/8, 716/5
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network. In accordance with the preferred embodiment of the present invention, the rules checker algorithm performs these tasks by: (1) analyzing each branch of the network to determine the primary RC delay of each branch assuming the branch being analyzed corresponds to the worst case RC delay of the network; (2) analyzing each branch of the network assuming one of the other branches of the network corresponds to the worst case RC delay of the network and determining the effect that the resistances and capacitances of the branch being analyzed would have on other branches; (3) determining the total effective RC delay of each branch by combining the primary RC delay of each branch with the effect that the other branches have on the branch being analyzed; and (4) determining which branch of the network has the largest total effective RC delay.

Claims

1. An apparatus for determining a total effective RC delay of each branch of a network and for determining which branch has the largest total effective RC delay, the network being comprised in an integrated circuit, each branch having a primary RC delay associated therewith, the primary RC delay of each branch being attributable to one or more resistances and one or more capacitances comprised by the branch, the apparatus comprising:

a computer programmed to execute a rules checker algorithm, wherein when the rules checker algorithm is executed by the computer, the rules checker algorithm analyzes each branch to determine a total effective RC delay of each branch, wherein the total effective RC delay of a particular branch includes the primary RC delay attributable to said one or more resistances and said one or more capacitances of the particular branch and an effect that said one or more resistances and said one or more capacitances of any other branches have on the particular branch, the rules checker algorithm determining which branch has the largest total effective RC delay.

2. The apparatus of claim 1, wherein the rules checker algorithm determines which branch of the network has the largest total effective RC delay by:

analyzing each branch and determining the primary RC delay associated with each branch;

analyzing each branch and determining the effect that said one or more resistances and said one or more capacitances of the branch being analyzed would have on other branches;

determining the total effective RC delay of each branch by combining the primary RC delay of each branch with the effect that said one or more resistances and said one or more capacitances of any other branch have on the branch associated with the primary RC delay; and

comparing the total effective RC delays of the branches to determine which of the branches has the largest total effective RC delay.

3. The apparatus of claim 2, wherein the network comprises a driver gate and first and second receiver gates, the first and second receiver gates each having an input that is electrically coupled by first and second branches, respectively, to an output of the driver gate, and wherein the rules checker algorithm traverses the branches and calculates the primary RC delay associated the branches.

4. The apparatus of claim 3, wherein the rules checker algorithm traverses the branches and calculates the effects that the resistances and capacitances of each branch has on the other branch.

5. The apparatus of claim 4, wherein the rules checker algorithm calculates the total effective RC delay of the first branch by combining the effect that said one or more resistances and capacitances of the second branch has on the first branch with the primary RC delay of the first branch, wherein the rules checker algorithm calculates the total effective RC delay of the second branch by combining an effect that said one or more resistances and capacitances of the second branch has on the first branch with the primary RC delay of the first branch.

6. The apparatus of claim 5, wherein the rules checker algorithm utilizes said one or more resistances of the first branch to obtain a first scaling factor, the rules checker algorithm processing said one or more capacitances of the first branch in accordance with the first scaling factor to obtain the effect that said one or more resistances and capacitances of the first branch will have on the second branch, and wherein the rules checker algorithm utilizes said one or more resistances of the second branch to obtain a second scaling factor, the rules checker algorithm processing said one or more capacitances of the second branch in accordance with the second scaling factor to obtain the effect that said one or more resistances of the second branch will have on the first branch.

7. The apparatus of claim 6, wherein the first and second scaling factors are stored in first and second address locations, respectively, in a lookup table, wherein the rules checker algorithm reads the first and second scaling factors out of said first and second addresses in the lookup table and processes said one or more capacitances of the first and second branches, respectively, in accordance with the scaling factors.

8. A method for determining a total effective RC delay associated with each branch of a network and for determining which branch has the largest total effective RC delay, the network being comprised in an integrated circuit, each branch having a primary RC delay associated therewith, the primary RC delay of a branch being associated with one or more resistances and one or more capacitances comprised by the branch, the method comprising the steps of:

analyzing each branch to determine a total effective RC delay of each branch, wherein the total effective RC delay of a particular branch includes the primary RC delay attributable to said one or more resistances and said one or more capacitances of the particular branch and an effect that said one or more resistances and capacitances of any other branches of the network have on the particular branch; and

determining which of the total effective RC delays is the largest.

9. The method of claim 8, wherein the analyzing step further comprises the steps of:

analyzing each branch and determining the primary RC delay associated with each branch;

analyzing each branch and determining the effect that said one or more resistances and capacitances of the branch being analyzed would have on other branches; and

analyzing each branch and determining the total effective RC delay of each branch by combining the primary RC delay of the branch being analyzed with the effect that said one or more resistances and capacitances of any other branch has on the branch being analyzed.

10. The method of claim 9, wherein the step of determining which branch has the largest total effective RC delay comprises the step of:

comparing the total effective RC delays of the branches to determine which of the branches has the largest total effective RC delay.

11. The method of claim 10, wherein the network comprises a driver gate and first and second receiver gates, each of the receiver gates having an input that is electrically coupled by first and second branches, respectively, to an output of the driver gate, and wherein, during the step of analyzing the branches to determine the primary RC delays, the first and second branches are traversed to obtain the values of the resistances and capacitances that are used to calculate the primary RC delays associated with the branches and to determine the effects that the resistances and capacitances of the branches have on other branches.

12. The method of claim 11, wherein the total effective RC delay of the first branch is determined by combining an effect that said one or more resistances and capacitances of the second branch has on the first branch with the primary RC delay of the first branch, and wherein the total effective RC delay of the second branch is determined by combining the effect that said one or more resistances and capacitances of the first branch has on the second branch with the primary RC delay of the second branch.

13. The method of claim 12, wherein the effect that the first branch has on the second branch is determined by utilizing said one or more resistances of the first branch to obtain a first scaling factor and by processing said one or more capacitances of the first branch in accordance with the first scaling factor to obtain the effect that the first branch will have on the second branch, and wherein the effect that the second branch has on the first branch is determined by utilizing said one or more resistances of the second branch to obtain a second scaling factor and by processing said one or more capacitances of the second branch in accordance with the second scaling factor to obtain the effect that the second branch will have on the first branch.

14. The method of claim 13, wherein said one or more resistances of the first and second branches are utilized to generate first and second addresses, respectively, of locations in a lookup table, the first scaling factor being stored in the first address location in the lookup table, the second scaling factor being stored in the second address location in the lookup table, wherein the first and second addresses are utilized to read the first and second scaling factors out of said first and second address locations in the lookup table.

15. A computer-readable medium having a computer program for determining a total effective RC delay associated with each branch of a network and for determining which branch has the largest total effective RC delay, the network being comprised in an integrated circuit, each branch having a primary RC delay associated therewith, the primary RC delay of a branch being associated with one or more resistances and one or more capacitances comprised by the branch, the computer program:

being embodied on a computer-readable medium, the program comprising;

a first code segment, the first code segment analyzing each branch to determine a total effective RC delay of each branch, wherein the total effective RC delay of a particular branch includes the primary RC delay attributable to said one or more resistances and said one or more capacitances of the particular branch and an effect that said one or more resistances and capacitances of any other branches of the network have on the particular branch; and

a second code segment, the second code segment determining which of the total effective RC delays is the largest.

16. The computer-readable medium of claim 15, wherein the first code segment comprises:

a third code segment, the third code segment analyzing each branch and determining the primary RC delay associated with each branch;

a fourth code segment, the fourth code segment analyzing each branch and determining the effect that said one or more resistances and capacitances of the branch being analyzed would have on other branches; and

a fifth code segment, the fifth code segment analyzing each branch and determining the total effective RC delay of each branch by combining the primary RC delay of the branch being analyzed with the effect that said one or more resistances and capacitances of any other branch has on the branch being analyzed.

17. The computer-readable medium of claim, 16, wherein the second code segment compares the total effective RC delays of the branches to determine which:

of the branches has the largest total effective RC delay.

18. The computer-readable medium of claim 17, wherein the network comprises a driver gate and first and second receiver gates, the first and second receiver gates having an input that is electrically coupled by first and second branches, respectively, to an output of the driver gate, and wherein the third code segment determines the primary RC delays of the first and second branches by traversing the branches to obtain the values of the resistances and capacitances and by using the values to calculate the primary RC delays associated with the branches.

19. The computer-readable medium of claim 18, wherein the fifth code segment determines the total effective RC delay of the first branch by combining the effect that said one or more resistances and capacitances of the second branch has on the first branch with the primary RC delay of the first branch, and wherein the fourth code segment determines the total effective RC delay of the second branch by combining the effect that said one or more resistances and capacitances of the first branch has on the second branch with the primary RC delay of the second branch.

20. The computer-readable medium of claim 19, and wherein the fourth code segment determines the effect that the first branch has on the second branch by utilizing said one or more resistances of the first branch to obtain a first scaling factor and by processing said one or more capacitances of the first branch in accordance with the first scaling factor to obtain the effect that the first branch will have on the second branch, and wherein the fourth code segment determines the effect that the second branch has on the first branch by utilizing said one or more resistances of the second branch to obtain a second scaling factor and by processing said one or more capacitances of the second branch in accordance with the second scaling factor to obtain the effect that the second branch will have on the first branch.