Microcomputer with multiple memories for storing data

• US 6,507,884 B1
• Filed: 12/22/1998
• Issued: 01/14/2003
• Est. Priority Date: 12/25/1997
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Hotaka, Kazuo, Yatsu, Tsunehiko, Chigira, Kazumasa, Kanahori, Norimasa
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/218,768
• Time in Patent Office: 1,484 Days
• Field of Search: 711/5, 711/103, 711/171-172, 710/66, 365/230.03, 365/230.04, 365/230.01, 365/238.5
• US Class Current: 711/5
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.

Claims

1. A microcomputer comprising:

M number of memories each having an N-bit width and identical addresses for storing program data being an N×

M width word in a shared manner;

a selection circuit for selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory; and

an addressing circuit for addressing the M number of memories based on an externally supplied address signal, wherein

data is sequentially written into the memory which was selectively placed in an enabled state; and

designation of an address of the M number of memories outputs addressed N bit datum from each of the M number of memories, each having an N-bit width, the outputted datum being combined to output a word having an M×

N width.

2. The microcomputer according to claim 1, wherein the externally supplied control signal is a most significant bit of the externally supplied address signal.

3. The microcomputer according to claim 1, wherein the selection circuit selectively chooses a memory according to an externally designation signal showing a writing mode, and places the M number of memories in an enabled state according to a designation signal showing a normal operation mode to cause the M number of memories to operate as a single memory of N×

M bits.

4. The microcomputer according to claim 1, wherein each of the memories is a nonvolatile memory capable of electrically and collectively erasing stored data.

5. The microcomputer according to claim 1, wherein data from a memory writer controller for N-bits can be written into the M number of memories.

6. The microcomputer according to claim 5, wherein the memory writer controller is reset at the start of writing the program data into the M number of memories.

7. The microcomputer according to claim 5, wherein the data written in the M number of memories is read and compared with data the memory writer controller writes.

8. A microcomputer comprising:

M number of memories each having an N-bit width and identical addresses for storing program data being an N×

M width word in a shared manner;

a selection circuit for selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory; and

an addressing circuit for addressing the M number of memories based on an externally supplied address signal, wherein

data is sequentially written into the memory which was selectively placed in an enabled state; and

designation of an address of the M number of memories outputs addressed N bit datum from each of the M number of memories, each having an N-bit width, the outputted datum being combined to output a word having an M×

N width.

9. The microcomputer according to claim 8, wherein the externally supplied control signal is a most significant bit of the externally supplied address signal.

10. The microcomputer according to claim 8, wherein the means for selectively placing chooses a memory according to an externally supplied designation signal showing a writing mode, and places the M number of memories in an enabled state according to a designation signal showing a normal operation mode to cause the M number of memories to operate as a single memory of N×

M bits.

11. The microcomputer according to claim 8, wherein each of the memories is a nonvolatile memory capable of electrically and collectively erasing stored data.

12. The microcomputer according to claim 8, wherein data from a memory writer controller for N-bits can be written into the M number of memories.

13. The microcomputer according to claim 12, wherein the memory writer controller is reset at the start of writing the program data into the M number of memories.

14. The microcomputer according to claim 12, wherein the data written in the M number of memories is read and compared with data the memory writer controller writes.

15. A method for writing data in a microcomputer comprising the steps of:

providing M number of memories each having an N-bit width and identical addresses for storing program data being an N×

M width word in a shared manner;

selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory;

addressing the M number of memories based on an externally supplied address signal;

sequentially writing data into the memory which was selectively placed in an enabled state; and

outputting addressed N bit datum from each of the M number of memories in response to designation of an address thereof, each having an N-bit width, and combining the outputted datum to output a word having an M×

N width.

16. The microcomputer according to claim 15 further comprising the step of choosing a memory according to an externally supplied designation signal showing a writing mode, and placing the M number of memories in an enabled state according to a designation signal showing a normal operation mode to cause the M number of memories to operate as a single memory of N×

M bits.

17. The microcomputer according to claim 15 further comprising the step of writing data from a memory writer controller for N-bits into the M number of memories.

18. The microcomputer according to claim 15 further comprising the step of writing data from a memory writer controller for N-bits into the M number of memories.

19. The microcomputer according to claim 18 further comprising the step of resetting the writer at the start of writing the program data into the M number of memories.

20. The microcomputer according to claim 18 further comprising the step of reading and comparing the data written in the M number of memories with data the memory writer controller writes.