Binary data memory design with data stored in low-power sense
First Claim
1. A read-only random-access memory design method comprising:
- determining a low-power sense for binary data having bit values;
storing said data in said low-power sense in a row-addressable memory array having rows and columns, each of said bit values being stored at a respective row and a respective column, said data being stored so that all bit values stored in a first column are inverted and all bit values stored in a second column are not inverted; and
inverting data output from one of said first and second columns and not inverting data output from the other of said columns.
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Abstract
A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.
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Citations
10 Claims
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1. A read-only random-access memory design method comprising:
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determining a low-power sense for binary data having bit values;
storing said data in said low-power sense in a row-addressable memory array having rows and columns, each of said bit values being stored at a respective row and a respective column, said data being stored so that all bit values stored in a first column are inverted and all bit values stored in a second column are not inverted; and
inverting data output from one of said first and second columns and not inverting data output from the other of said columns. - View Dependent Claims (2, 3, 4, 5)
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6. A read-only random access memory comprising:
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plural bit-value storage locations arranged in an array with rows and columns, each of said rows having an address;
an address input for receiving said addresses; and
a data output for outputting bit values stored in a row when its address is received by said address input, said data output including means for inverting some but not all of the bit values of said row. - View Dependent Claims (7, 8, 9, 10)
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Specification