Integrated multi-channel fiber channel analyzer

• US 6,507,923 B1
• Filed: 04/19/1999
• Issued: 01/14/2003
• Est. Priority Date: 04/19/1999
• Status: Expired due to Term

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: I-Tech Corporation (II-VI Incorporated)
• Inventors: Kuechle, Daniel G., Bucher, Steven, Wall, Timothy A., Seppanen, Eric D.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/294,935
• Time in Patent Office: 1,366 Days
• Field of Search: 714/717, 714/712, 714/821
• US Class Current: 714/712
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels. Analysis of the data captured by the integrated multi-channel analyzer is further enhanced by a processor resident in the cabinet that is connected by a data/control bus to each analyzer channel and by a hardware search engine associated with each trace buffer memory. The resident processor receives high level commands from a remote host processor and sends selected trace data to the remote host computer over an Ethernet connection.

Claims

1. An integrated multi-channel analyzer for a communication network comprising:

at least three analyzer channels, each analyzer channel including;

at least an input connection port to the communication network;

a trace buffer memory; and

logic circuitry that controls selective write operations of traces from the input connection port to the trace buffer memory in response to a status condition; and

a high speed status bus operably connected to the logic circuitry of each analyzer channel,

wherein the logic circuitry of each analyzer channel propagates the status condition for that analyzer channel to all other analyzer channels via the high speed status bus and the logic circuitry of each analyzer channel receives the status condition of all other analyzer channels and selectively incorporates the other status conditions as part of the status condition of that channel.

2. The integrated multi-channel analyzer of claim 1, wherein the communication network is a high bandwidth Fibre Channel communication network.

4. The integrated multi-channel analyzer of claim 2 wherein the analyzer channels are configured as a pair of analyzer channels on an analysis logic card, the analysis logic card including:

a pair of input connection ports and a pair of output connection ports to the communication network;

a pair of trace buffer memories;

a pair of channel logic circuits, each channel logic circuit controlling selective write operations of traces from one of the input connection ports to an associated one of the trace buffer memories in response to a status condition for that channel; and

a set of local interconnections between the pair of channel logic circuits on each analysis logic card separate from the first status bus and the second bus such that the logic circuit of one channel can access the trace buffer memory and the input connection port and output connection port of the other channel.

5. The integrated multi-channel analyzer of claim 4 wherein the input connection port and the output connection port are configured on a front end module operably connected to the analysis logic card and wherein the front end module includes a converter module to interface the ports of a channel with the communication network and circuitry that automatically wraps the input connection port of one channel to the output port connection of the other channel.

3. An integrated multi-channel analyzer for a communication network comprising:

a cabinet;

a processor housed within the cabinet having an external connection that receives high level commands for configuring and controlling the multi-channel analyzer;

at least three analyzer channels housed within the cabinet, each analyzer channel including;

at least an input connection port to the communication network;

a trace buffer memory; and

logic circuitry controlling selective write operations of traces from the input connection port to the trace buffer memory in response to a status condition for that channel that selectively incorporates a status condition of any other analyzer channel as part of the status condition of that channel; and

a first high speed status bus operably connected to each of the analyzer channels to propagate the status condition for each analyzer channel to all other analyzer channels; and

a second bus operably connected between each of the analyzer channels and the processor to send low level commands from the processor to the analyzer channels and to receive the output of selective read operations of traces in the trace buffer memories within the processor.

6. The integrated multi-channel analyzer of claim 3, wherein the communication network is a high bandwidth Fibre Channel communication network.

7. An integrated multi-channel analyzer for a communication network comprising:

a cabinet;

at least three analyzer channels housed within the cabinet, each analyzer channel including;

at least an input connection port to the communication network;

a trace buffer memory; and

logic circuitry that controls selective write operations of traces from the input connection port to the trace buffer memory in response to a status condition;

a resident processor housed within the chassis; and

a backplane electrically connecting the resident processor to the at least three analyzer channels, the backplane including a common clock signal whereby a single clock signal is utilized by the logic circuitry of all of the analyzer channels.

8. The integrated multi-channel analyzer of claim 7, wherein the communication network is a high bandwidth Fibre Channel communication network.

9. An integrated multi-channel analyzer for a communication network comprising:

a cabinet;

at least three analyzer channels housed within the cabinet, each analyzer channel including;

at least an input connection port to the communication network;

a trace buffer memory; and

logic circuitry that controls selective write operations of traces from the input connection port to a selected trace buffer memory, the selected trace buffer memory determined by a buffer full flag communicated by each analyzer channel to all of the other analyzer channels.

10. The integrated multi-channel analyzer of claim 9, wherein the communication network is a high bandwidth Fibe Channel communication network.

11. An integrated multi-channel analyzer for a communication network comprising:

at least three analyzer channels, each analyzer channel including;

at least an input connection port to the communication network;

a trace buffer memory; and

means for distributively controlling the operation of the analyzer channel in response to a status condition that selectively incorporates status conditions from all of the other analyzer channels.

12. The integrated multi-channel analyzer of claim 11, wherein the communication network is a high bandwidth Fibre Channel communication network.

13. A method for controlling the operation of at least three analyzer channels for analyzing a communication network, each analyzer channel including an input connection port, a trace buffer memory and logic circuitry, the method comprising:

a. connecting the input connection port of each analyzer channel to a unique node in the communication network;

b. using the analyzer channels to monitor frame data on the connection port at each node;

c. in response to a programmable first condition detected in the frame data by at least one of the analyzer channels, setting a first global flag that is communicated to all of the other analyzer channels;

d. in response to the first global flag, initiating detection of a programmable second condition in the frame data by at least another of the analyzer channels;

e. in response to the programmable second condition detected in the frame data by another of the analyzer channels, setting a second global flag that is communicated to all of the other analyzer channels; and

f. in response to the second global flag, triggering at least some of the analyzer channels to store frame data in the trace buffer memories.

14. The method of claim 13, wherein the communication network is a high bandwidth Fibre Channel communication network.

15. A method for controlling the operation of analyzer channels for analyzing a communication network, each analyzer channel including an input connection port, a trace buffer memory and logic circuitry, the method comprising:

a. connecting the input connection port of each analyzer channel to a unique node in the communication network;

b. distributing a common clock signal to clock the logic circuitry of all of the analyzer channels;

c. using the analyzer channels to monitor frame data on the connection port at each node;

d. downloading selected frame data in the trace buffer memories into the memory of a processor also clocked by the common clock signal; and

e. transmitting the selected frame data from the memory of the processor to a remote host computer.

16. The method of claim 15 wherein each analyzer channel includes a hardware search engine coupled to the trace buffer memory, and wherein the method further comprises:

c1. using the hardware search engine to identify selected frame data.

17. The method of claim 16 further comprising:

d1. initiating a time index of each of the trace buffer memories using the hardware search engine upon the completion of a trace; and

d2. using the time index to identify selected frame data in the trace buffer memories for downloading.

18. The method of claim 15, wherein the communication network is a high bandwidth Fibre Channel communication network.

19. A method for controlling the operation of multiple analyzer channels for analyzing a communication network, each analyzer channel including an input connection port, a trace buffer memory and logic circuitry, the method comprising:

a. connecting the input connection port of each analyzer channel to a unique node in the communication network;

b. using the analyzer channels to monitor frame data on the connection port at each node;

c. communicating a buffer full flag for each of the trace buffer memories to the logic circuitry of each of the analyzer channels; and

d. storing frame data in a selected trace buffer memory for each analyzer channel in response to a status condition as determined by the logic circuitry for that channel, wherein the logic circuitry utilizes the buffer full flags to determine the selected trace buffer memory into which the frame data will be stored.

20. The method of claim 19, wherein the communication network is a high bandwidth Fibre Channel communication network.