Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool

• US 6,507,938 B1
• Filed: 11/12/1999
• Issued: 01/14/2003
• Est. Priority Date: 11/12/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation, Shell Oil Company (Shell Plc)
• Original Assignee: Intel Corporation
• Inventors: Gopal, Nanda, Roy-Neogi, Kalapi
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US09/439,877
• Time in Patent Office: 1,159 Days
• Field of Search: 716/7, 716/10, 716/11, 716/1, 716/6, 716/8-9, 716/12-13, 716/17, 713/503
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool. According to one embodiment of the present invention cells of a circuit design are placed in a placement of an integrated circuit, and wires are routed between the cells to complete a layout of the integrated circuit having a number of nets. The placement is analyzed for timing performance, and an improved location is identified for each cell in the placement. The improved location is identified based on an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location and a net criticality of each net in the layout.

Claims

1. A method comprising:

placing cells of a circuit design in a placement of an integrated circuit;

analyzing the placement for timing performance comprising;

routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths;

defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints; and

for each net in the layout, calculating an effective delay caused by the net to a signal propagating through one of the critical signal paths having a slack that is less than a slack of other critical signal paths that also include the net comprising;

calculating a slack for each critical signal path in the layout including the net;

selecting one of the critical signal paths including the net and having a slack that is less than the slack of each other critical signal path that also includes the net;

calculating an effective delay to a propagation of an input signal through the selected critical signal path caused by the net in the selected critical signal path; and

selecting the effective delay caused by the net to the propagation of the input signal through the selected critical signal path as a delay caused by the net in the layout; and

rearranging the cells to improve a timing performance of the integrated circuit based on the analysis of the placement.

2. The method of claim 1 wherein calculating a slack for each critical signal path comprises:

calculating a signal path response for each critical signal path in the layout including the net; and

calculating a slack for each critical signal path in the layout including the net as a difference between an actual delay caused by the critical signal path to a propagation of a signal and its timing constraint, the slack of the critical signal path being positive if the actual delay is less than the timing constraint, and the slack of the critical signal path being negative if the actual delay is longer than the timing constraint.

3. The method of claim 1 wherein calculating an effective delay further comprises:

defining the input signal with a slope to be received by the selected critical signal path; and

for each net in the selected critical signal path;

calculating a delay caused by a driver cell receiving the input signal in the net as a function of the slope of the input signal and a total load capacitance of the net;

calculating a slope of an output signal generated by the driver cell as a function of the slope of the input signal and the total load capacitance of the net;

calculating a delay caused by wires in the net as a function of the slope of the output signal with a distributed lumped RC model of the wires;

calculating an effective delay caused by the net as a sum of the delay caused by the driver cell and a delay caused by the wires; and

redefining the output signal as an input signal to a succeeding net in the selected critical signal path.

4. A method comprising:

placing cells of a circuit design in a placement of an integrated circuit;

routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths; and

analyzing the placement for timing performance comprising;

defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints;

calculating an actual delay caused by each critical signal path in the layout to a propagation of a signal through the critical signal path; and

calculating a slack for each critical signal path in the layout as a difference between the actual delay caused by the critical signal path to a propagation of a signal and its timing constraint, the slack of the critical-signal path being positive if the actual delay is less than the timing constraint, and the slack of the critical signal path being negative if the actual delay is longer than the timing constraint; and

for each cell in the placement identifying an improved location for the cell based on;

an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location; and

a net criticality of each net in the layout.

5. The method of claim 4, further comprising:

identifying the improved location for the cell based on a number of critical signal paths including the net, the estimated savings, and the net criticality; and

calculating the net criticality of each net in the layout based on;

a slack criticality of the net; and

a wire criticality of the net.

6. The method of claim 5, further comprising:

calculating the slack criticality of each net in the layout comprising;

selecting a critical signal path including the net for which the actual delay is longer than the timing constraint by the greatest amount; and

calculating the slack criticality to be proportional to a difference between the actual delay and the timing constraint for the selected critical signal path; and

calculating the wire criticality of each net in the layout as a ratio of a capacitance of wires in the net to a capacitance of pins in the net.

7. The method of claim 4, further comprising calculating the estimated savings for each cell in the placement comprising:

identifying available locations for the cell; and

for each available location;

estimating a delay caused by a driver cell for each net in the layout when the cell is placed in the location;

estimating a delay caused by wires in each net in the layout when the cell is placed in the location;

estimating an effective delay caused by each net in the layout when the cell is placed in the location as a sum of the estimated delay caused by the wires and the estimated delay caused by the driver cell; and

calculating the estimated savings for each net in the layout when the cell is placed in the location as a difference between the estimated effective delay and the actual delay for each net in the layout.

8. A computer-readable medium having computer-readable instructions for performing a method comprising:

placing cells of a circuit design in a placement of an integrated circuit; and

analyzing the placement for timing performance comprising;

routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths;

defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints; and

for each net in the layout, calculating an effective delay caused by the net to a signal propagating through one of the critical signal paths having a slack that is less than a slack of other critical signal paths that also include the net comprising;

calculating a slack for each critical signal path in the layout including the net;

selecting one of the critical signal paths including the net and having a slack that is less than the slack of each other critical signal path that also includes the net;

calculating an effective delay to a propagation of an input signal through the selected critical signal path caused by the net in the selected critical signal path; and

selecting the effective delay caused by the net to the propagation of the input signal through the selected critical signal path as a delay caused by the net in the layout; and

rearranging the cells to improve a timing performance of the integrated circuit based on the analysis of the placement.

9. The computer-readable medium of claim 8 wherein calculating a slack for each critical signal path comprises:

calculating a signal path response for each critical signal path in the layout including the net; and

calculating a slack for each critical signal path in the layout including the net as a difference between an actual delay caused by the critical signal path to a propagation of a signal and its timing constraint, the slack of the critical signal path being positive if the actual delay is less than the timing constraint, and the slack of the critical signal path being negative if the actual delay is longer than the timing constraint.

10. The computer-readable medium of claim 8 wherein calculating an effective delay further comprises:

defining the input signal with a slope to be received by the selected critical signal path; and

for each net in the selected critical signal path;

calculating a delay caused by a driver cell receiving the input signal in the net as a function of the slope of the input signal and a total load capacitance of the net;

calculating a slope of an output signal generated by the driver cell as a function of the slope of the input signal and the total load capacitance of the net;

calculating a delay caused by wires in the net as a function of the slope of the output signal with a distributed lumped RC model of the wires;

calculating an effective delay caused by the net as a sum of the delay caused by the driver cell and a delay caused by the wires; and

redefining the output signal as an input signal to a succeeding net in the selected critical signal path.

11. A computer-readable medium having computer-readable instructions for performing a method comprising:

placing cells of a circuit design in a placement of an integrated circuit;

routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths;

analyzing the placement for timing performance comprising;

defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints;

calculating an actual delay caused by each critical signal path in the layout to a propagation of a signal through the critical signal path; and

calculating a slack for each critical signal path in the layout as a difference between the actual delay caused by the critical signal path to a propagation of a signal and its timing constraint, the slack of the critical signal path-being positive if the actual delay is less than the timing constraint, and the slack of the critical signal path being negative if the actual delay is longer than the timing constraint; and

for each cell in the placement identifying an improved location for the cell based on;

an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location; and

a net criticality of each net in the layout.

12. The computer-readable medium of claim 11, further comprising computer-readable instructions for:

identifying the improved location for the cell based on a number of critical signal paths including the net, the estimated savings, and the net criticality; and

calculating the net criticality of each net in the layout based on;

a slack criticality of the net; and

a wire criticality of the net.

13. The computer-readable medium of claim 12, further comprising computer-readable instructions for:

calculating the slack criticality of each net in the layout comprising;

selecting a critical signal path including the net for which the actual delay is longer than the timing constraint by the greatest amount; and

calculating the slack criticality to be proportional to a difference between the actual delay and the timing constraint for the selected critical signal path; and

calculating the wire criticality of each net in the layout as a ratio of a capacitance of wires in the net to a capacitance of pins in the net.

14. The computer-readable medium of claim 11, further comprising computer-readable instructions for calculating the estimated savings for each cell in the placement comprising:

identifying available locations for the cell; and

for each available location;

estimating a delay caused by a driver cell for each net in the layout when the cell is placed in the location;

estimating a delay caused by wires in each net in the layout when the cell is placed in the location;

estimating an effective delay caused by each net in the layout when the cell is placed in the location as a sum of the estimated delay caused by the wires and the estimated delay caused by the driver cell; and

calculating the estimated savings for each net in the layout when the cell is placed in the location as a difference between the estimated effective delay and the actual delay for each net in the layout.

15. A method of analyzing a placement of cells of a circuit design for timing performance comprising:

routing wires between the cells to complete a layout of the integrated circuit having a plurality of nets and signal paths, each signal path comprising a sequential ordering of one or more of the nets and cells occurring alternately, each net and each cell being included in one or more of the signal paths;

defining critical signal paths in the layout as being one or more of the signal paths having respective timing constraints; and

for each net in the layout, calculating an effective delay caused by the net to a signal propagating through one of the critical signal paths having a slack that is less than a slack of other critical signal paths that also include the net comprising;

calculating a slack for each critical signal path in the layout including the net;

selecting one of the critical signal paths including the net and having a slack that is less than the slack of each other critical signal path that also includes the net;

calculating an effective delay to a propagation of an input signal through the selected critical signal path caused by the net in the selected critical signal path; and

selecting the effective delay caused by the net to the propagation of the input signal through the selected critical signal path as a delay caused by the net in the layout.

16. The method of claim 15 wherein calculating an effective delay further comprises:

defining the input signal with a slope to be received by the selected critical signal path; and

for each net in the selected critical signal path;

calculating a delay caused by a driver cell receiving the input signal in the net as a function of the slope of the input signal and a total load capacitance of the net;

calculating a slope of an output signal generated by the driver cell as a function of the slope of the input signal and the total load capacitance of the net;

calculating a delay caused by wires in the net as a function of the slope of the output signal with a distributed lumped RC model of the wires;

calculating an effective delay caused by the net as a sum of the delay caused by the driver cell and a delay caused by the wires; and

redefining the output signal as an input signal to a succeeding net in the selected critical signal path.

17. The method of claim 15 wherein calculating a slack for each critical signal path comprises:

calculating a signal path response for each critical signal path in the layout including the net; and

calculating a slack for each critical signal path in the layout including the net as a difference between an actual delay caused by the critical signal path to a propagation of a signal and its timing constraint, the slack of the critical signal path being positive if the actual delay is less than the timing constraint, and the slack of the critical signal path being negative if the actual delay is longer than the timing constraint.