Methods and circuits for testing a circuit fabrication process for device uniformity
First Claim
1. A method for measuring feature-size uniformity across a surface of a programmable logic device, wherein the programmable logic device is configurable using a collection of configurable elements to provide specified logic functions, the method comprising:
- a. configuring a first set of the configurable elements in a first region of the programmable logic device to include a first oscillator, wherein the first oscillator oscillates at a first frequency that depends upon a first device having a first critical dimension;
b. configuring a second set of the configurable elements in a second region of the programmable logic device to include a second oscillator, wherein the second oscillator oscillates at a second frequency that depends upon a second device having a second critical dimension;
c. measuring a difference between the first and second frequencies to obtain a frequency difference; and
d. correlating the frequency difference to an extent of feature-size uniformity, the greater the frequency difference, the less the feature-size uniformity.
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Abstract
Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.
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Citations
26 Claims
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1. A method for measuring feature-size uniformity across a surface of a programmable logic device, wherein the programmable logic device is configurable using a collection of configurable elements to provide specified logic functions, the method comprising:
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a. configuring a first set of the configurable elements in a first region of the programmable logic device to include a first oscillator, wherein the first oscillator oscillates at a first frequency that depends upon a first device having a first critical dimension;
b. configuring a second set of the configurable elements in a second region of the programmable logic device to include a second oscillator, wherein the second oscillator oscillates at a second frequency that depends upon a second device having a second critical dimension;
c. measuring a difference between the first and second frequencies to obtain a frequency difference; and
d. correlating the frequency difference to an extent of feature-size uniformity, the greater the frequency difference, the less the feature-size uniformity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for measuring feature-size uniformity across a surface of an integrated circuit, the method comprising:
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a. forming a first oscillator in a first region and a second oscillator in a second region, wherein the first oscillator oscillates at a first frequency that depends upon a first device having a first critical dimension, and wherein the second oscillator oscillates at a second frequency that depends upon a second device having a second critical dimension;
b. measuring a difference between the first and second frequencies to obtain a frequency difference; and
c. correlating the frequency difference to an extent of feature-size uniformity, the greater the frequency difference, the less the feature-size uniformity. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A system for measuring feature-size uniformity across a surface of an integrated circuit, the system comprising:
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a. a first oscillator located in a first region of the integrated circuit, the first oscillator producing a first output signal on a first oscillator output terminal, wherein the first output signal oscillates at a first frequency that depends upon a first critical dimension of devices within the first region;
b. a second oscillator located in a second region of the integrated circuit, the second oscillator producing a second output signal on a second oscillator output terminal, wherein the second output signal oscillates at a second frequency that depends upon a second critical dimension of devices within the second region; and
c. a processor having an input port connected to the first and second oscillator output terminals, the processor adapted to derive the first and second critical dimensions using the first and second frequencies. - View Dependent Claims (19, 20, 21, 22)
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23. A computer-readable medium having computer-executable instructions for performing the steps of:
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a. configuring a programmable logic device to include a plurality of oscillators, each oscillator being formed using configurable logic resources in a respective one of a plurality of regions of the programmable logic device;
b. monitoring an output frequency for each of the plurality of oscillators to obtain a plurality of output frequencies, there being at least one output frequency for each of the plurality of regions of the programmable logic device; and
c. correlating the at least one output frequency for each region of the programmable logic device to a critical dimension in each region of the programmable logic device.
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24. A method of measuring feature-size uniformity on an integrated circuit, the method comprising:
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a. defining a plurality of regions on the surface of the integrated circuit, each of the regions including a plurality of devices;
b. measuring the switching speeds of the devices;
c. correlating the switching speeds of the plurality of devices in a first one of the plurality of regions with a first critical dimension; and
d. correlating the switching speeds of the plurality of devices in a second one of the plurality of regions with a second critical dimension. - View Dependent Claims (25, 26)
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Specification