Methods and circuits for testing a circuit fabrication process for device uniformity

• US 6,507,942 B1
• Filed: 07/11/2000
• Issued: 01/14/2003
• Est. Priority Date: 07/11/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wang, Feng, Calderone, Anthony P., La, Tho Le
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LEVIN, NAUM B
• Application Number:
  US09/613,494
• Time in Patent Office: 917 Days
• Field of Search: 716/1-21, 714/30, 712/1, 712/34, 712/36, 712/37, 712/39, 712/43, 703/14, 703/19, 703/23, 375/354, 375/142, 369/53, 368/113, 326/40, 177/210.FP
• US Class Current: 714/30
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.

Claims

1. A method for measuring feature-size uniformity across a surface of a programmable logic device, wherein the programmable logic device is configurable using a collection of configurable elements to provide specified logic functions, the method comprising:

a. configuring a first set of the configurable elements in a first region of the programmable logic device to include a first oscillator, wherein the first oscillator oscillates at a first frequency that depends upon a first device having a first critical dimension;

b. configuring a second set of the configurable elements in a second region of the programmable logic device to include a second oscillator, wherein the second oscillator oscillates at a second frequency that depends upon a second device having a second critical dimension;

c. measuring a difference between the first and second frequencies to obtain a frequency difference; and

d. correlating the frequency difference to an extent of feature-size uniformity, the greater the frequency difference, the less the feature-size uniformity.

2. The method of claim 1, wherein the programmable logic device is manufactured using a sequence of mask steps, the method further comprising adjusting the sequence of mask steps to minimize the difference between the first and second critical dimensions.

3. The method of claim 2, further comprising manufacturing a second programmable logic device using the adjusted sequence of mask steps.

4. The method of claim 3, further comprising measuring feature-size uniformity across a second surface of the second programmable logic device using the method of claim 3.

5. The method of claim 1, wherein the first and second oscillators are ring oscillators.

6. The method of claim 1, wherein the programmable logic device is an FPGA.

7. The method of claim 1, further comprising mapping the first and second regions on the surface of the programmable logic device.

8. The method of claim 7, the mapping further comprising indicating the relative values of the first and second critical dimensions.

9. A method for measuring feature-size uniformity across a surface of an integrated circuit, the method comprising:

a. forming a first oscillator in a first region and a second oscillator in a second region, wherein the first oscillator oscillates at a first frequency that depends upon a first device having a first critical dimension, and wherein the second oscillator oscillates at a second frequency that depends upon a second device having a second critical dimension;

b. measuring a difference between the first and second frequencies to obtain a frequency difference; and

c. correlating the frequency difference to an extent of feature-size uniformity, the greater the frequency difference, the less the feature-size uniformity.

10. The method of claim 9, wherein the integrated circuit is fabricated using a sequence of masks, and wherein the masks define the first and second critical dimensions as equal.

11. The method of claim 10, the method further comprising adjusting the sequence of mask steps to minimize the difference between the first and second critical dimensions.

12. The method of claim 11, further comprising manufacturing a second integrated circuit using the adjusted sequence of mask steps.

13. The method of claim 12, further comprising measuring feature-size uniformity across a second surface of the second integrated circuit using the method of claim 9.

14. The method of claim 9, wherein the first and second oscillators are ring oscillators.

15. The method of claim 9, wherein the integrated circuit is bounded by scribe lines, and wherein the first and second oscillators at least partially overlap the scribe lines.

16. The method of claim 9, further comprising mapping the first and second regions on the surface of the integrated circuit.

17. The method of claim 16, the mapping further comprising indicating the relative values of the first and second critical dimensions.

18. A system for measuring feature-size uniformity across a surface of an integrated circuit, the system comprising:

a. a first oscillator located in a first region of the integrated circuit, the first oscillator producing a first output signal on a first oscillator output terminal, wherein the first output signal oscillates at a first frequency that depends upon a first critical dimension of devices within the first region;

b. a second oscillator located in a second region of the integrated circuit, the second oscillator producing a second output signal on a second oscillator output terminal, wherein the second output signal oscillates at a second frequency that depends upon a second critical dimension of devices within the second region; and

c. a processor having an input port connected to the first and second oscillator output terminals, the processor adapted to derive the first and second critical dimensions using the first and second frequencies.

19. The system of claim 18, the processor being further adapted to display the relative locations of the first and second regions on the surface of the integrated circuit.

20. The system of claim 19, wherein the display of the relative locations of the first and second regions includes indications of the relative values of the first and second critical dimensions.

21. The system of claim 18, wherein the integrated circuit further comprises a counter having a counter input terminal connected to the first oscillator output terminal, and a counter output terminal connected to the input port of the processor, such that the input port of the processor connects to the first oscillator output terminal via the counter.

22. The system of claim 21, wherein the integrated circuit further comprises a second counter having a second counter input terminal connected to the second oscillator output terminal, and a second counter output terminal connected to the input port of the processor, such that the input port of the processor connects to the second oscillator output terminal via the second counter.

23. A computer-readable medium having computer-executable instructions for performing the steps of:

a. configuring a programmable logic device to include a plurality of oscillators, each oscillator being formed using configurable logic resources in a respective one of a plurality of regions of the programmable logic device;

b. monitoring an output frequency for each of the plurality of oscillators to obtain a plurality of output frequencies, there being at least one output frequency for each of the plurality of regions of the programmable logic device; and

c. correlating the at least one output frequency for each region of the programmable logic device to a critical dimension in each region of the programmable logic device.

24. A method of measuring feature-size uniformity on an integrated circuit, the method comprising:

a. defining a plurality of regions on the surface of the integrated circuit, each of the regions including a plurality of devices;

b. measuring the switching speeds of the devices;

c. correlating the switching speeds of the plurality of devices in a first one of the plurality of regions with a first critical dimension; and

d. correlating the switching speeds of the plurality of devices in a second one of the plurality of regions with a second critical dimension.

25. The method of claim 24, further comprising defining a known relationship between switching speed and critical dimension, wherein the step of correlating the switching speeds of the plurality of devices in a first one of the plurality of regions comprises applying the known relationship to the switching speeds of the plurality of devices in the first one of the plurality of regions.

26. The method of claim 24, wherein measuring the switching speeds of the devices comprises configuring the devices as oscillators and measuring at least one of the period or the frequency of the oscillators.