Inspectable buried test structures and methods for inspecting the same

• US 6,509,197 B1
• Filed: 08/25/2000
• Issued: 01/21/2003
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Pinto, Gustavo A., Mantalas, Lynda C., Richardson, Neil, Long, Robert Thomas, Satya, Akella V. S.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US09/648,212
• Time in Patent Office: 879 Days
• Field of Search: 438/14, 438/12, 438/17, 714/724, 324/158.1
• US Class Current: 438/12
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

Claims

1. A method of testing a semiconductor die, the semiconductor die having a substrate, a first metal layer and a second metal layer formed over the first metal layer, the method comprising:

a. forming a first metal test structure in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection;

b. forming a second metal test structure in the second metal layer of the semiconductor die such that the second metal test structure has a second portion and a second electrical connection to the first metal test structure; and

c. determining whether the first metal test structure is intact between the first electrical connection and the second electrical connection by performing a voltage contrast inspection,

wherein the second electrical connection is designed to have a significantly different potential during the voltage contrast inspection than the second portion of the second metal structure.

4. The method of claim 1 wherein each of the first electrical connection and the second electrical connection comprises a via.

5. The method of claim 1 wherein the first metal test structure is an extended metal line between the first electrical connection and the second electrical connection.

6. The method of claim 1 wherein step c comprises scanning the second metal test structure with an electron beam.

2. A method of testing a semiconductor die, the semiconductor die having a substrate, a first metal layer and a second metal layer formed over the first metal layer, the method comprising:

a. forming a first metal test structure in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection;

b. forming a second metal test structure in the second metal layer of the semiconductor die such that the second metal test structure has a a second electrical connection to the first metal test structure, wherein the second electrical connection is formed at a distance from the first electrical connection; and

c. determining whether the first metal test structure is intact between the first electrical connection and the second electrical connection by evaluating the extent electrical current can pass from the second metal test structure to the first connection, wherein the second metal test structure, except for the second electrical connection, is floating.

3. A method as recited in claim 2 further comprising forming a damascene oxide between the second electrical connection and the rest of the second metal test structure.

7. A method of claim of testing a semiconductor die, the semiconductor die having a substrate, a first metal layer and a second metal layer formed over the first metal layer, the method comprising:

a. forming a first metal test structure in the first metal layer of the semiconductor die such that the first metal test structure has a first electrical connection;

b. forming a second metal test structure in the second metal layer of the semiconductor die such that the second metal test structure has a second electrical connection to the first metal test structure, wherein the second electrical connection is formed at a distance from the first electrical connection; and

c. determining whether the first metal test structure is intact between the first electrical connection and the second electrical connection by evaluating the extent electrical current can pass from the second metal test structure to the first connection, wherein the first electrical connection couples the first metal test structure to the substrate.

8. A method of fabricating a test structure, comprising:

forming a voltage contrast test structure element;

forming at least one nonconductive layer over at least a portion of the test structure element; and

forming at least one conductive element within the nonconductive layer, wherein the conductive element is electrically coupled with voltage contrast test structure,

wherein the conductive element comprises a conductive plug.

9. The method of claim 8, wherein the nonconductive layer prevents voltage contrast testing of the covered portion of the voltage contrast test structure except through the conductive element.

10. The method of claim 8, wherein the conductive element is comprised of a plurality of stacked conductive plugs.

11. The method of claim 8, further comprising exposing the conductive element to an incident beam, and voltage contrast testing the portion of the voltage contrast test structure.

12. The method of claim 11, wherein the conductive element is used to assist in locating a defect buried below the nonconductive layer.

13. A method of verifying quality of a product, comprising:

obtaining data concerning product quality that was produced by subjecting voltage contrast test structures present on the product to voltage contrast testing during manufacturing of the product; and

re-inspecting at least a portion of voltage contrast structures present on the product prior to product acceptance, thereby producing additional data representing product quality.

14. The method of claim 13, wherein at least a portion of the data or the additional data represents expected reliability of the product.

16. The method of claim 13, wherein the additional data is used to verify the accuracy of the obtained data.

20. The method of claim 13, wherein the step of re-inspecting is performed by probing the portion of voltage contrast structures.

15. A method of verifying quality of a product, comprising:

obtaining data concerning product quality that was produced by subjecting voltage contrast test structures present on the product to voltage contrast testing during manufacturing of the product; and

re-inspecting at least a portion of voltage contrast structures present on the product prior to product acceptance, thereby producing additional data representing product quality, wherein the step of re-inspecting is performed by a prospective purchaser of the product.

17. The method of claim 15, wherein the additional data is used as an acceptance criterion for the product.

19. The method of claim 15, wherein the obtained data or the additional data is used to predict yield of the product.

18. A method of verifying quality of a product, comprising:

obtaining data concerning product quality that was produced by subjecting voltage contrast test structures present on the product to voltage contrast testing during manufacturing of the product; and

re-inspecting at least a portion of voltage contrast structures present on the product prior to product acceptance, thereby producing additional data representing product quality, wherein the additional data is used to set a price for the product.

21. A method of forming a test structure for testing for defects in a first metal layer of a semiconductor die having a substrate, the method comprising:

forming a lower test structure element;

forming a nonconductive layer over at least a portion of the lower test structure element;

forming an upper test structure element at a higher level than at least a portion of the lower test structure element; and

forming a conductive element within the nonconductive layer, wherein the conductive element is electrically coupled with the lower test structure element and the upper test structure element, wherein the conductive element comprises a conductive plug.

22. The method of claim 21 further comprising performing voltage contrast on the conductive element to determine whether the lower test structure has a defect.

23. The method of claim 21 further comprising:

forming a plurality of lower test structure elements and a plurality of upper test structure elements, wherein the lower test structure elements are formed within a same first conductive layer and the upper test structure elements are formed within a same second conductive layer, the upper and lower test structure elements being chained together by a plurality of conductive elements within the nonconductive layer.

24. The method of claim 23 wherein a first end of the chain is a selected one of either the upper test structure or lower test structure, the method further comprising coupling the first end to a predefined voltage level, further comprising performing a voltage contrast inspection on a second end of the chain that is opposite the first end, the second end being coupled with a selected one of the upper test structure elements, the voltage contrast inspection being performed to determine whether there is a break within the chain of upper and lower test structures.