Inexpensive, reliable, planar RFID tag structure and method for making same
First Claim
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1. A process for making an RFID tag on a plastic or glass or plastic laminated to glass substrate, comprising the steps of:
- 1) forming an antenna for an RFID tag on a plastic or glass or plastic laminated to glass substrate;
2) using a flat panel display manufacturing machine or any machine capable of performing the same functions as a flat panel display manufacturing machine on a plastic, glass or plastic laminated to glass substrate to perform processing to form an integrated circuit RFID tag transceiver with an antenna port on a plastic or glass or plastic laminated to glass substrate; and
3) electrically connecting said antenna port of said RFID tag transceiver to said antenna;
wherein said step
2) comprises;
forming a first layer of insulating material on both surfaces of said substrate, said first layer of insulating material having a thickness and Young'"'"'s modulus which is selected in light of the thickness and Young'"'"'s modulus of said substrate so as to reduce differential strain to a level which will not cause failure of said substrate or any structure formed on said substrate at anticipated temperatures to be encountered in the future;
forming a layer of amorphous semiconductor on said first layer of insulating material;
forming gate insulator layer;
forming layer of gate conductor material over said gate insulator layer;
photolithographically etching to form the gate islands of one or more transistors to expose at least areas of said layer of amorphous semiconductor where source and drain doping is to occur;
crystallizing and doping the amorphous silicon semiconductor to form source and drain regions for each transistor thereby leaving an undoped semiconductor region below each island;
etching to form thin film transistor islands to isolate each transistor from the others;
forming an insulating layer over all the transistors formed on said substrate and etching via holes therein to allow contacts to source and drain regions and the gate of each transistor;
forming a layer of conductive material to fill all via holes and make electrical contact with said source, drain and gate structures of each transistor;
etching said layer of conductive material to form the pattern of electrical connections between source, drain and gate structures of said transistors to form said RFID tag transceiver circuit and to form antenna contact leader lines;
forming a layer of insulation over said pattern of electrical connections and forming via holes where contacts to said antenna contact leader lines can be made; and
forming a conductive antenna pattern over said layer of insulation over said pattern of electrical connections so as to make electrical contact with said antenna contact leader lines.
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Abstract
Process and device structures for constructing RFID tag and smart card and toy controller integrated circuit transceivers built inexpensively using flat panel display manufacturing machines on large plastic or glass or plastic laminated to glass substrates using thin film technologies at low temperatures and using chemicals and gases which will not attack or damage the substrate. Also disclosed are structures to eliminate the reliability problems caused by differential strain caused by different coefficients of thermal expansion.
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Citations
18 Claims
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1. A process for making an RFID tag on a plastic or glass or plastic laminated to glass substrate, comprising the steps of:
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1) forming an antenna for an RFID tag on a plastic or glass or plastic laminated to glass substrate;
2) using a flat panel display manufacturing machine or any machine capable of performing the same functions as a flat panel display manufacturing machine on a plastic, glass or plastic laminated to glass substrate to perform processing to form an integrated circuit RFID tag transceiver with an antenna port on a plastic or glass or plastic laminated to glass substrate; and
3) electrically connecting said antenna port of said RFID tag transceiver to said antenna;
wherein said step
2) comprises;
forming a first layer of insulating material on both surfaces of said substrate, said first layer of insulating material having a thickness and Young'"'"'s modulus which is selected in light of the thickness and Young'"'"'s modulus of said substrate so as to reduce differential strain to a level which will not cause failure of said substrate or any structure formed on said substrate at anticipated temperatures to be encountered in the future;
forming a layer of amorphous semiconductor on said first layer of insulating material;
forming gate insulator layer;
forming layer of gate conductor material over said gate insulator layer;
photolithographically etching to form the gate islands of one or more transistors to expose at least areas of said layer of amorphous semiconductor where source and drain doping is to occur;
crystallizing and doping the amorphous silicon semiconductor to form source and drain regions for each transistor thereby leaving an undoped semiconductor region below each island;
etching to form thin film transistor islands to isolate each transistor from the others;
forming an insulating layer over all the transistors formed on said substrate and etching via holes therein to allow contacts to source and drain regions and the gate of each transistor;
forming a layer of conductive material to fill all via holes and make electrical contact with said source, drain and gate structures of each transistor;
etching said layer of conductive material to form the pattern of electrical connections between source, drain and gate structures of said transistors to form said RFID tag transceiver circuit and to form antenna contact leader lines;
forming a layer of insulation over said pattern of electrical connections and forming via holes where contacts to said antenna contact leader lines can be made; and
forming a conductive antenna pattern over said layer of insulation over said pattern of electrical connections so as to make electrical contact with said antenna contact leader lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
forming a first insulating layer on top and bottom surfaces of said substrate on which said transceiver is formed in step
2), said first insulating layer having a thickness and being of a material or combination of materials which is selected to have a Young'"'"'s modulus so as to, in light of the thickness and Young'"'"'s modulus of said substrate, substantially reduce any difference between strain of said first insulating layer and said substrate on which said transceiver is formed;
forming an antenna conductor over said first insulating layer with contact pads to which electrical contact to said antenna may be made;
forming a second layer of insulating material over said antenna conductor and contact pads and photolithographically etching via holes therein to allow electrical contact to be made to said antenna contact pads;
forming a layer of conductive material over said second insulating layer and etching away all conductive material on horizontal surfaces of said second insulating layer to leave said via holes filled with electrically conductive material;
forming a layer of amorphous semiconductor over said second layer of insulating material;
forming a layer of gate oxide over said layer of amorphous semiconductor;
forming a layer of conductive gate material over said gate oxide;
photolithographically etching one or more gate islands in said gate oxide and said layer of conductive gate material;
doping and crystallizing source and drain regions in said amorphous semiconductor layer which are self aligned with each said gate island thereby leaving an undoped semiconductor region between each gate island;
photolithographically etching through at least said amorphous semiconductor layer to define the lateral extents of each source and drain region to define a thin film transistor island around each gate island;
forming a third insulating layer over the top of the structure formed so far to insulate each source, drain and gate of each thin film transistor formed;
forming via holes in said third insulating layer to expose at least a part of the gate of each said thin film transistor and the source and drain regions that are necessary to be connected to form said RFID tag transceiver; and
forming a pattern of conductive material that fills said via holes and connects together said thin film transistors in such a way as to form said RFID tag transceiver.
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13. The process of claim 12 wherein said step of photolithographically etching said one or more gate islands is an anisotropic etch to allow greater density of transistor structures to be formed.
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14. The process of claim 12 wherein said processing to form said antenna comprises forming said antenna photolithographically.
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15. The process of claim 12 wherein said processing to form said antenna comprises forming said antenna by silk screening said antenna on a layer of insulation formed over said inexpensive substrate.
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16. The process of claim 12 wherein said processing to form said antenna comprises forming said antenna by sputter deposition or electroplating of a layer of insulation formed over said inexpensive substrate and then photolithographically etching said antenna pattern to make a series of planar loops.
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17. The process of claim 2 further comprising the step of cyrstallizing said layer of amorphous semiconductor layer after it is deposited and before any transistor soure and drain regions are formed therein.
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18. A process for manufacturing an RFID tag integrated circuit including MOS transistors and EEPROM nonvolatile cells on an plastic, glass or plastic laminated to glass substrate comprising:
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inserting an plastic, glass or plastic laminated to glass substrate into a flat panel display manufacturing machine or other machine capable of performing processing carried out by flat panel display manufacturing machines;
using a flat panel display manufacturing machine or any machine capable of performing the same functions as a flat panel display manufacturing machine on a plastic, glass or plastic laminated to glass substrate to perform a process defined by a recipe file that defines processing steps, gases and etchants that comprise a recipe to form thin film MOS transistors and/or EEPROM nonvolatile memory cells, said process comprising the following steps;
depositing a first layer of insulating material on both top and bottom surfaces of said plastic, glass or plastic laminated to glass substrate, said first insulating layer having a thickness and being of a material or combination of materials having a Young'"'"'s Modulus which are selected in light of the thickness and Young'"'"'s Modulus of said plastic, glass or plastic laminated to glass substrate so as to substantially reduce difference in strain between said plastic, glass or plastic laminated to glass substrate and said first layer of insulating material;
depositing a layer of amorphous semiconductor over said first insulating layer;
masking off areas of said integrated circuit where EEPROM cells are to be formed, and depositing a layer of gate insulator;
masking off areas where MOS transistors of said RFID tag transceiver are being formed to expose areas where EEPROM memory cells are to be formed and depositing one or more layers of gate insulator to form an insulation layer that is to lie below the floating gate;
depositing a layer of gate conductor;
masking off locations where MOS transistors are being formed to leave exposed only locations where EEPROM memory cells are being formed, and depositing a layer of intergate insulator from which will be formed the insulation layer between the floating gate and the control gate of each EEPROM cell;
forming a conductive layer from which the control gate of all EEPROM memory cells is to be formed;
photolithographically etching gate islands at both said MOS transistor and EEPROM cell locations;
doping and crystallizing source and drain regions in said amorphous semiconductor layer so as to be self aligned with said gate islands of all said MOS transistors and EEPROM memory cells;
photolithographically etching to define the lateral extents of each thin film transistor island at each MOS transistor and EEPROM memory cell;
depositing an insulation layer over all MOS transistors and EEPROM memory cells and etching vias therethrough for source, drain, gate and control gate contacts at all MOS transistor and EEPROM cell locations;
depositing and photolithographically patterning a conductive contact pattern that fills said via holes and conects all the MOS transistors and EEPROM cells together to form an RFID tag transceiver with nonvolatile memory and contact pads for an antenna port for connecting to an antenna;
forming a conductive antenna on the same substrate as said transceiver and which is electrically connected to said contact pads of said antenna port of said transceiver.
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Specification