Method of fabricating a high-voltage transistor

• US 6,509,220 B2
• Filed: 05/02/2002
• Issued: 01/21/2003
• Est. Priority Date: 11/27/2000
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/137,625
• Publication Number:
  US 20020132405A1
• Time in Patent Office: 264 Days
• Field of Search: 438/186, 438/188, 438/197, 438/199, 438/301, 438/305, 438/306, 438/526, 438/527, 438/529
• US Class Current: 438/197
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

forming a first epitaxial layer of a first conductivity type on a substrate of a second conductivity type;

implanting a first dopant in the first epitaxial layer to form a first buried layer of the second conductivity type;

forming a second epitaxial layer of the first conductivity type on an upper surface of the first epitaxial layer; and

implanting a second dopant in the second epitaxial layer to form a second buried layer of the second conductivity type.

2. The method according to claim 1 wherein the first and second buried layers being disposed at different vertical depths relative to an upper surface of the second epitaxial layer such that a JFET conduction channel of the first conductivity type is formed between the first and the second buried layers.

3. The method according to claim 1 wherein the first buried layer is spaced apart from an upper surface of the substrate.

4. The method according to claim 1 wherein the second buried layer is spaced apart from the upper surface of the second epitaxial layer.

5. The method according to claim 1 wherein the first and second dopants are identical.

6. The method according to claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type.

7. The method according to claim 1 wherein the first and second buried layers are spaced vertically apart in a substantially parallel configuration.

8. The method according to claim 1 further comprising, prior to implanting the first dopant in the first epitaxial layer, forming a first mask layer on the upper surface of the first epitaxial layer, the first mask layer having a first thickness and a second thickness.

9. The method according to claim 1 further comprising, prior to implanting the second dopant in the second epitaxial layer, forming a second mask layer on the upper surface of the second epitaxial layer, the second mask layer having a first thickness and a second thickness.

10. The method according to claim 1 wherein the implanting of the first dopant in the first epitaxial layer is performed successively at different energies to produce one or more additional buried layers in the first epitaxial layer, each of the one or more additional buried layers being disposed at different vertical depths relative to the upper surface of the first epitaxial layer.

11. The method according to claim 1 wherein the implanting of the second dopant in the second epitaxial layer is performed successively at different energies to produce one or more additional buried layers in the second epitaxial layer, each of the one or more additional buried layers being disposed at different vertical depths relative to the upper surface of the second epitaxial layer.

12. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

forming a well region of a first conductivity type in a substrate of a second conductivity type;

implanting a first dopant in the well region to form a first buried layer of the second conductivity type;

forming an epitaxial layer of the first conductivity type on an upper surface of the substrate;

implanting a second dopant in the epitaxial layer to form a second buried layer of the second conductivity type.

13. The method according to claim 12 wherein the first and second buried layers being disposed at different vertical depths relative to an upper surface of the epitaxial layer such that a JFET conduction channel of the first conductivity type is formed between the first the second buried layers.

14. The method according to claim 12 wherein the first buried layer is spaced apart from the upper surface of the substrate.

15. The method according to claim 12 wherein the second buried layer is spaced apart from the upper surface of the epitaxial layer.

16. The method according to claim 12 wherein the first and second buried layers are spaced vertically apart in a substantially parallel configuration.

17. The method according to claim 12 wherein the first conductivity type is N-type and the second conductivity type is P-type.

18. The method according to claim 12 wherein the implanting of the first dopant is performed successively at different energies to produce one or more additional buried layers in the well region, each of the one or more additional buried layers being disposed at different vertical depths relative to the upper surface of the substrate.

19. The method according to claim 12 wherein the implanting of the second dopant in the epitaxial layer is performed successively at different energies to produce one or more additional buried layers in the epitaxial layer, each of the one or more additional buried layers being disposed at different vertical depths relative to the upper surface of the epitaxial layer.

20. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

successively implanting ions in a laterally extended region and a source region of a first epitaxial layer having a first conductivity type, each implant being performed at a different energy to form a first plurality of buried layers in the laterally extended region and a second plurality of buried layers in the source region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the first epitaxial layer;

forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;

successively implanting ions in a laterally extended region and a source region of the second epitaxial layer, each implant being performed at a different energy to form a third plurality of buried layers in the laterally extended region and a fourth plurality of buried layers in the source region, each of the third plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the second epitaxial layer;

forming a gate insulated from the second epitaxial layer by a dielectric layer;

forming a body region of the second conductivity type, the body region adjoining the dielectric layer;

forming a source diffusion region of the first conductivity type in the body region; and

forming a drain diffusion region of the first conductivity type in the second epitaxial layer.

21. The method according to claim 20 further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

22. The method according to claim 20 wherein a section of the source region of the first epitaxial layer is partially masked at the upper surface during implantation such that the second plurality of buried layers in the source region is formed into a first continuous doped region.

23. The method of claim 22 wherein a section of the source region of the second epitaxial layer is partially masked at the upper surface such that the fourth plurality of buried layers in the source region is formed into a second continuous doped region, the first and second continuous doped regions being connected to form a single continuous doped region.

24. The method according to claim 20 wherein the third plurality of buried layers is spaced-apart from the body region.

25. The method according to claim 20 wherein the first and third plurality of buried layers are spaced-apart from the single continuous doped region.

26. The method according to claim 20 wherein the gate comprises a trench gate structure.

27. The method according to claim 20 wherein the gate comprises a planar gate structure.

28. A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

successively implanting ions in a laterally extended region of a first epitaxial layer having a first conductivity type, each implant being performed at a different energy to form a first plurality of buried layers in the laterally extended region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the first epitaxial layer;

forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;

successively implanting ions in a laterally extended region of the second epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the second epitaxial layer;

forming a gate insulated from the second epitaxial layer by a dielectric layer;

forming a body region of the second conductivity type adjoining the dielectric layer;

forming a source diffusion region of the first conductivity type in the body region; and

forming a drain diffusion region of the first conductivity type in the second epitaxial layer.

29. The method according to claim 28 further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

30. The method according to claim 28 wherein the gate comprises a trench gate structure.

31. The method according to claim 28 wherein the gate comprises a planar gate structure.

32. The method according to claim 28 wherein the second plurality of buried layers are spaced-apart from the body region.

33. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

forming a first epitaxial layer of a first conductivity type on a substrate of a second conductivity type;

successively implanting a first dopant in the first epitaxial layer, each implant being performed at a different energy to form a first plurality of buried layers, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the first epitaxial layer;

forming an epitaxial layer of the first conductivity type on an upper surface of the first epitaxial layer;

successively implanting a second dopant in the second epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers within the second epitaxial layer, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the second epitaxial layer.

34. The method according to claim 33 wherein the first and second dopants are identical.

35. The method according to claim 33 wherein the first conductivity type is N-type and the second conductivity type is P-type.

36. The method according to claim 33 wherein the first and second plurality of buried layers are spaced vertically apart in a substantially parallel configuration.

37. The method according to claim 33 further comprising, prior to implanting the first dopant in the first epitaxial layer, forming a first mask layer on the upper surface of the first epitaxial layer, the first mask layer having a first thickness and a second thickness.

38. A method of fabricating a high-voltage field-effect transistor (HVFET), comprising:

forming a well region of a first conductivity type in a substrate of a second conductivity type;

successively implanting a first dopant into the well region, each implant being performed at a different energy to form a first plurality of buried layers in the well region;

forming an epitaxial layer of the first conductivity type on the substrate;

successively implanting a second dopant in a laterally extended region and a source region of the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region and a third plurality of buried layers in the source region;

forming a gate insulated from the epitaxial layer by a dielectric layer;

forming a source diffusion region of the first conductivity type; and

forming a drain diffusion region of the first conductivity type.

39. The method of claim 38 further comprising:

forming a body region of the second conductivity type, wherein the second plurality of buried layers being spaced-apart from the body region.

40. The method of claim 38 wherein each of the first plurality of buried layers are of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the substrate such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the well region.

41. The method of claim 38 wherein each of the second plurality of buried layers are of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the epitaxial layer.

42. The method according to claim 38 further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

43. The method according to claim 38 wherein a section of the source region of the epitaxial layer is partially masked at the upper surface during implantation such that the third plurality of buried layers in the source region is formed into a continuous doped region.

44. The method according to claim 42 wherein the first and second plurality of buried layers are spaced-apart from the continuous doped region.

45. The method of claim 38 wherein the gate comprises a trench gate structure.

46. A method of fabricating a high-voltage field-effect transistor (HVFET), comprising:

forming a well region of a first conductivity type on a substrate of a second conductivity type;

successively implanting ions in the well region, each implant being performed at a different energy to form a first plurality of buried layers, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the substrate such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the well region;

forming an epitaxial layer of the first conductivity type on the substrate;

successively implanting ions in a laterally extended region of the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the epitaxial layer;

forming a gate insulated from the epitaxial layer by a dielectric layer, the gate extending over the upper surface adjacent the laterally extended region of the epitaxial layer;

forming a source diffusion region of the first conductivity type in the body region; and

forming a drain diffusion region of the first conductivity type in the epitaxial layer.

47. The method according to claim 46 further comprising:

forming a body region of the second conductivity type, the body region adjoining the dielectric layer.

48. The method according to claim 46 further comprising:

forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

49. The method according to claim 46 wherein the gate comprises a trench gate structure.

50. A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

forming a well region of a first conductivity type in a substrate of a second conductivity type;

successively implanting a first dopant in the well region, each implant being performed at a different energy to form a first plurality of buried layers in the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the substrate such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed;

forming an epitaxial layer of the first conductivity type on the upper surface of the substrate;

successively implanting ions a second dopant in the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the epitaxial layer, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the epitaxial layer.

51. The method according to claim 50 wherein the first and second plurality of buried layers are formed in a substantially parallel configuration.

52. The method according to claim 50 wherein each of the second plurality of buried layers is spaced apart from the upper surface of the epitaxial layer.

53. The method according to claim 50 wherein each of the first plurality of buried layers is spaced apart from the upper surface of the substrate.

54. The method according to claim 50 wherein the first conductivity type is N-type and the second conductivity type is P-type.

55. The method according to claim 50 wherein the first and second dopants are identical.

56. The method according to claim 50 further comprising, prior to implanting the first dopant in the well region, forming a first mask layer on the upper surface of the substrate, the first mask layer having a first thickness and a second thickness.