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Process for manufacturing electronic devices comprising nonvolatile memory cells of reduced dimensions

  • US 6,509,222 B1
  • Filed: 11/22/2000
  • Issued: 01/21/2003
  • Est. Priority Date: 11/26/1999
  • Status: Expired due to Term
First Claim
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1. A process for manufacturing electronic devices including memory cells, comprising:

  • on a substrate of semiconductor material, forming stacks including a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material;

    forming a protective layer of insulating material extending on top of said substrate and between said stacks, said protective layer having a height at least equal to that of said stacks;

    wherein forming stack structures comprises defining said floating gate region, said intermediate dielectric region, and said control gate region in two non-parallel directions so that each control gate region is separate and electrically insulated with respect to the control gate regions belonging to adjacent stack structures;

    such that, during said forming a protective layer, said stack structures are completely isolated with respect to one another in said two directions;

    and further comprising, after forming said stack structures, forming word lines of conductive material that extend above said protective layer and that are in electrical contact with said control gate regions.

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