Process for protecting array top oxide

• US 6,509,226 B1
• Filed: 09/27/2000
• Issued: 01/21/2003
• Est. Priority Date: 09/27/2000
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), Infineon Technologies AG
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Jaiprakash, Venkatachalam C., Mandelman, Jack, Divakaruni, Ramachandra, Malik, Rajeev, Seitz, Mihel
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/670,741
• Time in Patent Office: 846 Days
• Field of Search: 438/243-249, 438/386-392
• US Class Current: 438/243
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.

Claims

1. In a process for protecting an array top oxide layer in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays in a silicon substrate, the improvement comprising the step of depositing a thin polysilicon or amorphous silicon layer over the top oxide layer which serves as an etch stop and protects the underlying top oxide layer from etch damage, and planarizing an array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide prior to the depositing the thin polysilicon or amorphous silicon layer over the top oxide layer.

2. The process of claim 1, further comprising the steps of:

depositing an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack over the thin polysilicon or amorphous silicon layer;

opening the AA pad nitride to the silicon surface of the substrate;

etching shallow trench isolation (STI) to form isolation trenches;

filling the isolation trenches with high density plasma (HDP) oxide; and

planarizing to the top surface of the AA pad nitride and stripping the AA pad nitride, with the thin polysilicon or amorphous silicon layer serving as an etch stop protecting the underlying top oxide thereby avoiding thinning of the top oxide and preventing word line to substrate shorts and/or leakage.

3. A process for protecting an array top oxide in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic access memory (DRAM) arrays in a silicon substrate, comprising the steps of:

planarizing an array gate conductor (GC) polysilicon of the vertical MOSFET to a top surface of the top oxide;

depositing a thin polysilicon layer over the planarized surface;

depositing an active area (AA) pad nitride mask and tetraethyl orthosilicate (TEOS) stack;

using the AA pad nitride mask to open a pad layer to the silicon surface of the substrate;

performing shallow trench isolation (STI) etching to form isolation trenches;

filling the isolation trenches with high density plasma (HDP) oxide and planarizing to a top surface of the AA pad nitride mask;

stripping the AA pad nitride mask, with the thin polysilicon layer serving as an etch stop protecting the underlying top oxide;

depositing an etch support (ES) nitride liner, patterning an ES mask to open support areas, and etching the ES nitride liner, thin polysilicon layer and top oxide from exposed areas; and

using an etch array (EA) mask, opening the support gate polysilicon in the array, and removing the ES nitride liner selective to the underlying polysilicon layer, protecting the top oxide.