Method of reducing electromigration in copper lines by calcium-doping copper surfaces in a chemical solution

• US 6,509,262 B1
• Filed: 11/30/2000
• Issued: 01/21/2003
• Est. Priority Date: 11/30/2000
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lopatin, Sergey
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US09/728,684
• Time in Patent Office: 782 Days
• Field of Search: 438/687, 438/658, 438/660, 438/675, 438/678, 438/633, 438/638, 438/FOR.355, 438/FOR.348
• US Class Current: 438/658
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor device having copper (Cu) interconnect lines, formed in vias, whose surfaces are selectively doped with calcium (Ca) ions for preventing electromigration and a device thereby formed. The present invention method reduces electromigration in Cu interconnect lines by restricting Cu diffusion pathways along the interconnect surface. This diffusion restriction is achieved by selectively doping the Cu interconnect surfaces with Ca ions from a chemical solution. The present invention also provides a method of fabricating a semiconductor device, having a contaminant-reduced Cu—Ca/Cu interconnect line structure for reducing electromigration, improving interconnect reliability, and preventing corrosion, the method comprising: (a) providing a semiconductor substrate; (b) depositing a Cu interconnect line on the semiconductor substrate; (c) treating the Cu interconnect line in a chemical solution for facilitating selective doping of the Cu interconnect line with at least one plurality of ions selected from a group of ions consisting essentially of Cu ions and Ca ions, thereby selectively forming a Cu—Ca—X film on the Cu interconnect line, wherein X denotes at least one contaminant; (d) processing the Cu—Ca—X film by sputtering under an argon (Ar) atmosphere, thereby removing the at least one contaminant, and thereby effecting a thin Cu—Ca film on the Cu interconnect line; (e) annealing the thin Cu—Ca film, whereby the thin Cu—Ca film is alloyed, thereby forming a contaminant-reduced Cu—Ca alloy surface on the Cu interconnect line, and thereby forming a contaminant-reduced Cu—Ca/Cu interconnect line structure, comprising the contaminant-reduced Cu—Ca alloy surface, on the semiconductor substrate; and (f) completing formation of the semiconductor device.

Claims

1. A method of fabricating a semiconductor device having a contaminant-reduced copper-calcium alloy on copper (Cu—

Ca/Cu) interconnect line structure formed in a via for reducing electromigration therein, comprising;

a. providing a semiconductor substrate having the via;

b. depositing a copper (Cu) interconnect line in the via;

c. treating the Cu interconnect line in a chemical solution for facilitating selective doping of the Cu interconnect line with copper (Cu) and calcium (Ca), thereby selectively forming a Cu—

Ca—

X film on the Cu interconnect line, wherein X denotes at least one contaminant;

d. processing the Cu—

Ca—

X film by sputtering under an argon (Ar) atmosphere, thereby removing the at least one contaminant, and thereby effecting a thin Cu—

Ca film on the Cu interconnect line;

e. annealing the thin Cu—

Ca film, whereby the thin Cu—

Ca film is alloyed, thereby forming a contaminant-reduced Cu—

Ca alloy surface on the Cu interconnect line, and thereby forming the contaminant-reduced Cu—

Ca/Cu interconnect line structure, comprising the contaminant-reduced Cu—

Ca alloy surface on the semiconductor substrate; and

f. completing formation of the semiconductor device.

2. A method, as recited in claim 1,

wherein the depositing step (b) is performed by a technique selected from a group consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), and plasma enhanced chemical vapor deposition (PECVD), and

wherein the Cu interconnect line is dual inlaid.

3. A method, as recited in claim 1, wherein the chemical solution comprises an electroless plating solution, and wherein the electroless plating solution comprises:

a. at least one solvent;

b. at least one Cu salt;

c. at least one Ca salt;

d. at least one complexing agent; and

e. at least one reducing agent, (b) through (e) being dissolved in (a).

4. A method, as recited in claim 3, wherein the electroless plating solution further comprises:

f. at least one pH adjuster; and

g. at least one surfactant, (f) and (g) being dissolved in (a).

5. A method, as recited in claim 1, wherein the at least one contaminant is selected from a group consisting essentially of carbon (C), sulphur (S), and oxygen (O).

6. A method, as recited in claim 1, wherein the annealing step (e) is performed in a temperature range of 250°

C. to 450°

C. in an environment selected from a group consisting essentially of a vacuum, an inert gas, and a reducing ambient.

7. A method, as recited in claim 1, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a range of 0.2 atomic % to 5 atomic %.

8. A method, as recited in claim 3, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a range of 0.2 atomic % to 5 atomic %.

9. A method, as recited in claim 4, wherein the Cu—

Ca alloy surface is Cu-rich with a Ca-doping level in a range of 0.2 atomic % to 5 atomic %.

10. A method of fabricating a semiconductor device having a contaminant-reduced copper-calcium alloy on copper (Cu—

Ca/Cu) interconnect structure formed in a via for reducing electromigration therein, as described in claim 1,

a. providing a semiconductor substrate having the via;

b. depositing a dual inlaid copper (Cu) interconnect line in the via by a technique selected from a group consisting essentially of electroplating, electroless plating, chemical vapor deposition (CVD), plasma vapor deposition (PVD), and plasma enhanced chemical vapor deposition (PECVD);

c. treating the dual inlaid Cu interconnect line in an electroless plating solution for facilitating selective doping of the dual inlaid Cu interconnect line with copper (Cu) and calcium (Ca), the solution comprising;

(1) at least one solvent;

(2) at least one Cu salt;

(3) at least one Ca salt;

(4) at least one complexing agent;

(5) at least one reducing agent;

(6) at least one pH adjuster; and

(7) at least one surfactant,

(2) through (7) being dissolved in (1),

thereby selectively forming a Cu—

Ca—

X film on the dual inlaid Cu interconnect line, wherein X denotes at least one contaminant selected from a group consisting essentially of carbon (C), sulphur (S), and oxygen (O);

d. processing the Cu—

Ca—

X film by sputtering under an argon (Ar) atmosphere, thereby removing at least one contaminant from the Cu—

Ca—

X film, and thereby effecting a thin Cu—

Ca film on the dual inlaid Cu interconnect line;

e. annealing the thin Cu—

Ca film in a temperature range of 250°

C. to 450°

C. in an environment selected from a group consisting essentially of a vacuum, an inert gas, and a reducing ambient,

whereby the thin Cu—

Ca film is alloyed,

thereby forming a contaminant-reduced Cu—

Ca alloy surface onto the dual inlaid Cu interconnect line, the contaminant-reduced Cu—

Ca alloy surface being Cu-rich and having a Ca-doping level in a range of 0.2 atomic % to 5 atomic %, and

thereby forming the contaminant-reduced Cu—

Ca/Cu interconnect structure, comprising the contaminant-reduced Cu—

Ca alloy surface on the semiconductor substrate; and

f. completing formation of the semiconductor device.