Method to form self-aligned silicide with reduced sheet resistance

• US 6,509,264 B1
• Filed: 03/30/2000
• Issued: 01/21/2003
• Est. Priority Date: 03/30/2000
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Lin, Yung Tao, Li, Weining
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US09/537,480
• Time in Patent Office: 1,027 Days
• Field of Search: 438/305, 438/596, 438/585, 438/655, 438/618, 438/683, 438/664, 438/682
• US Class Current: 438/682
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer

Abstract

A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and silicon to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the device.

Claims

1. A method to form self-aligned silicide with reduced sheet resistance in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

depositing a polysilicon layer overlying said semiconductor substrate;

patterning said polysilicon layer to form polysilicon lines;

forming dielectric sidewall spacers by a method consisting of;

depositing a dielectric layer overlying said polysilicon lines and said semiconductor substrate;

polishing down said dielectric layer to expose the top surface of said polysilicon lines; and

thereafter anisotropically etching down said dielectric layer to form said dielectric sidewall spacers covering a lower portion of the vertical sidewalls of said polysilicon lines while exposing an upper portion of the vertical sidewalls of said polysilicon lines;

depositing a metal layer overlying said polysilicon lines, said dielectric sidewall spacers, and said semiconductor substrate and thereby forming contact surfaces between said metal layer and said exposed top surfaces of said polysilicon lines and between said metal layer and said exposed portions of said vertical sidewalls of said polysilicon lines;

annealing the integrated circuit device to react said metal layer and said polysilicon layer to selectively form a silicide layer in the surface of said polysilicon layer at said contact surfaces; and

removing remaining metal layer to complete said self-aligned silicide in the manufacture of said integrated circuit device.

2. The method according to claim 1 wherein said dielectric layer comprises one of the group of:

silicon dioxide and silicon nitride.

3. The method according to claim 1 wherein said dielectric layer is deposited to a thickness of between about 100 Angstroms and 5,000 Angstroms.

4. The method according to claim 1 wherein said step of polishing down said dielectric layer is by a chemical mechanical polish.

5. The method according to claim 1 wherein said exposed portions of said vertical sidewalls of said polysilicon lines have a vertical length of between about 100 Angstroms and 5,000 Angstroms.

6. The method according to claim 1 wherein said metal layer comprises one of the group of:

titanium and cobalt.

7. The method according to claim 1 wherein said silicide layer is formed to a thickness of between about 100 Angstroms and 3,000 Angstroms.

8. The method according to claim 1 wherein said polysilicon lines form gate electrodes for MOS transistors.

9. A method to form MOS transistors with self-aligned silicide in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

forming a gate oxide layer overlying said semiconductor substrate;

depositing a polysilicon layer overlying said gate oxide layer;

patterning said polysilicon layer and said gate oxide layer to form gates;

thereafter implanting ions into said semiconductor substrate to form lightly doped drain regions;

thereafter forming dielectric sidewall spacers by a method consisting of;

depositing a dielectric layer overlying said gates and said semiconductor substrate;

polishing down said dielectric layer to expose the top surface of said gates; and

thereafter anisotropically etching down said dielectric layer to form said dielectric sidewall spacers covering a lower portion of the vertical sidewalls of said gates while exposing an upper portion of the vertical sidewalls of said gates;

thereafter implanting ions into said semiconductor substrate to form source and drain regions;

thereafter depositing a metal layer overlying said gates, said dielectric sidewall spacers, and said semiconductor substrate and thereby forming contact surfaces between said metal layer and said exposed top surfaces of said gates, between said metal layer and said exposed portions of said vertical sidewalls of said gates, and between said metal layer and said semiconductor substrate in said source and drain regions;

annealing the integrated circuit device to react said metal layer and said polysilicon layer and to react said metal layer and said semiconductor substrate to selectively form a silicide layer in the surface of said polysilicon layer and in the surface of said semiconductor substrate at said contact surfaces; and

removing remaining metal layer to complete said MOS transistors with self-aligned silicide in the manufacture of said integrated circuit device.

10. The method according to claim 9 wherein said dielectric layer comprises one of the group of:

silicon dioxide and silicon nitride.

11. The method according to claim 9 wherein said dielectric layer is deposited to a thickness of between about 100 Angstroms and 5,000 Angstroms.

12. The method according to claim 9 wherein said step of polishing down said dielectric layer is by a chemical mechanical polish.

13. The method according to claim 9 wherein said exposed portions of said vertical sidewalls of said gates have a vertical length of between about 100 Angstroms and 5,000 Angstroms.

14. The method according to claim 9 wherein said metal layer comprises one of the group of:

titanium and cobalt.

15. The method according to claim 9 wherein said silicide layer has a thickness of between about 100 Angstroms and 3,000 Angstroms.

16. A method to form self-aligned silicide with reduced sheet resistance in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

depositing a polysilicon layer overlying said semiconductor substrate;

patterning said polysilicon layer to form polysilicon lines;

forming dielectric sidewall spacers by a method consisting of;

depositing a dielectric layer overlying said polysilicon lines and said semiconductor substrate wherein said dielectric layer comprises one of the group of;

silicon dioxide and silicon nitride;

polishing down said dielectric layer to expose the top surface of said polysilicon lines; and

thereafter anisotropically etching down said dielectric layer to form said dielectric sidewall spacers covering a lower portion of the vertical sidewalls of said polysilicon lines while exposing an upper portion of the vertical sidewalls of said polysilicon lines;

depositing a metal layer overlying said polysilicon lines, said dielectric sidewall spacers, and said semiconductor substrate and thereby forming contact surfaces between said metal layer and said exposed top surfaces of said polysilicon lines and between said metal layer and said exposed portions of said vertical sidewalls of said polysilicon lines;

annealing the integrated circuit device to react said metal layer and said polysilicon layer to selectively form a silicide layer in the surface of said polysilicon layer at said contact surfaces; and

removing remaining metal layer to complete said self-aligned silicide in the manufacture of said integrated circuit device.

17. The method according to claim 16 wherein said dielectric layer is deposited to a thickness of between about 100 Angstroms and 5,000 Angstroms.

18. The method according to claim 16 wherein said step of polishing down said dielectric layer is by a chemical mechanical polish.

19. The method according to claim 16 wherein said exposed portions of said vertical sidewalls of said polysilicon lines have a vertical length of between about 100 Angstroms and 5,000 Angstroms.

20. The method according to claim 16 wherein said polysilicon lines form gate electrodes for MOS transistors.