Semiconductor device with reduced source diffusion distance and method of making same

• US 6,509,607 B1
• Filed: 02/17/2000
• Issued: 01/21/2003
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Zetec Incorporated (Roper Technologies, Inc.)
• Original Assignee: Zetex Plc (Diodes Incorporated)
• Inventors: Jerred, Paul Antony
• Primary Examiner(s): Cao, Phat X.
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/505,808
• Time in Patent Office: 1,069 Days
• Field of Search: 257/330, 257/329, 257/212, 257/133, 257/220, 257/242, 257/263, 257/302, 257/326, 257/332, 257/368, 257/333, 257/334, 257/335, 257/338, 438/339, 438/206, 438/212, 438/259
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations extending into and through the body region such that lower side walls of each indentation are defined by portions of the body and drain regions and upper side walls of each indentation are defined by the source region. A lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer. A source conductor overlies the upper surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region. The source conductor extends into all upper portion of each indentation to contact portions of the upper side Walls of the indentation which are defined by the source regions.

Claims

1. A semiconductor device comprising a drain region, a body region overlying the drain region and defining an upper surface, source regions extending from adjacent the upper surface of the body region towards the drain region, and a series of indentations having side walls extending into and through the body region in a direction substantially perpendicular to the upper surface defined by the body region such that lower portions of the side walls of each indentation are defined by portions of the body and drain regions and upper portions of the side walls of each indentation are defined by the source regions, wherein a lower portion of each indentation is filled with a gate region isolated from the side walls by a first insulating layer and covered by a second insulating layer, a source conductor overlies the upper surface and is electrically connected to the source regions, and a gate conductor is electrically connected to each gate region, the source conductor extending into an upper portion of each indentation to contact portions of the upper portions of the side walls of the indentation which are defined by the source regions.

2. A device according to claim 1, wherein the upper surface of the body region is substantially planar and the source regions define upper surfaces which are substantially coplanar with the upper surface of the body region, the source conductor overlying and electrically contacting the upper surfaces of the source regions.

3. A device according to claim 2, wherein the upper surface of each source region has a width of less than 1 μ

m.

4. A device according to claim 3, wherein the upper surface of each source region leas a width of 0.4 μ

m.

5. A device according to claim 1, wherein the portions of the upper portions of the side walls of each indentation which are defined by the source regions and are contacted by the source conductor have a depth of 0.6 μ

m.

6. A device according to claim 1, wherein the upper surface of the body region incorporates a surface dopant concentration enhancement region.

7. A device according to claim 1, wherein the drain region is of n type conductivity, the body region is of p type conductivity, and the source regions are of n+ type conductivity.

8. A method for forming a semiconductor device according to claim 1, wherein indentations are formed in a surface of a semiconductor wafer such that the indentations have side walls extending in a substantially perpendicular direction from the surface, and are lined with a first insulating layer, and partially filled with a gate material such that lower portions of the side walls of each indentation adjacent the gate material are defined by portions of a body region and a drain region and upper portions of the side walls of each indentation above the gate material are defined by portions of source regions, a second insulating layer is formed in each indentation to cover the gate region, the second insulating layer is etched back to a depth such that portions of the upper portions of the side walls defined by the source regions are exposed above the second insulating layer, and an electrically conductive layer is deposited on the wafer so as to extend into each indentation and contact the exposed upper portions of the side walls defined by the source regions.

9. A method according to claim 8, wherein the second insulating layer is formed so as to fill each indentation above the gate material and to cover the upper surface of the wafer, the upper surface of the second insulating layer is planarised, and the planarised second insulating layer is etched back into the indentations.

10. A method according to claim 9, Wherein the second insulating layer is planarised by applying a further layer thereto such that the further layer has a planar upper surface, and then etching the resultant structure using an etchant which removes the material of the second insulating layer and the further layer at the same rate.

11. A device according to claim 1, wherein the source conductor has a generally planar surface that extends into an upper portion of each indentation, and contacts each source region on a generally planar surface of said source regions, whereby the resulting contact surface between said generally planar surfaces defines said upper portions of the side walls of each indentation.

12. A device according to claim 11 wherein the upper portions of the side-walls of each indentation are generally coplanar to the lower portions of the side-walls of said indentation.

13. A device according to claim 1, wherein each source region has a side surface defining the upper portions of the side wall of an indentation and an upper surface, whereby said source conductor extends into an upper portion of each indentation and contacts both the side surface and upper surface of each source region.

14. A device according to claim 1, wherein an upper surface defined by the gate region is substantially parallel to the upper surface defined by the body region.