Insulated gate semiconductor device with high minority carrier injection and low on-voltage by enlarged pn-junction area

• US 6,509,610 B2
• Filed: 07/18/2001
• Issued: 01/21/2003
• Est. Priority Date: 07/28/2000
• Status: Expired due to Fees

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Kawahashi, Akira, Nishiwaki, Katsuhiko
• Primary Examiner(s): Chaudhurl, Olik
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US09/906,825
• Publication Number:
  US 20020013030A1
• Time in Patent Office: 552 Days
• Field of Search: 257/330, 257/267, 257/328, 257/329, 257/331, 257/334, 257/339, 257/341, 257/342, 257/332, 257/244, 257/284, 257/314, 257/409, 257/374
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device is formed such that a contact surface between a p-type high-concentration semiconductor region and an n-type high-concentration buffer region assumes a convexo-concave shape. This makes it possible to enlarge an area of the contact surface between the p-type high-concentration semiconductor region and the n-type high-concentration buffer region. As a result, holes are injected into an n-type low-concentration drift region from the p-type high-concentration semiconductor region with higher efficiency and with a less voltage drop between the pn-junction. Thus, effects of conductivity modulation can be achieved sufficiently and the on-resistance and the voltage drop of an IGBT can be lowered.

Claims

1. A trench-gate-type semiconductor device comprising:

a first conductive-type semiconductor region having a first surface and a second surface opposite to the first surface, and made from a first conductive-type semiconductor material into which carriers are injected from a channel formed of a gate electrode formed in a trench solely on the first surface;

a second conductive-type semiconductor region made from a second conductive-type semiconductor material and formed in such a manner as to contact the second surface of the first conductive-type semiconductor region; and

a convexo-concave portion formed on a contact surface between the first and second conductive-type semiconductor regions.

2. The semiconductor device according to claim 1, wherein the contact surface is at least partially formed as a curved surface.

3. The semiconductor device according to claim 1, wherein the first conductive-type semiconductor region has a high-concentration impurity layer demonstrating a high concentration of impurities and a low-concentration impurity layer formed on the high-concentration impurity layer and demonstrating a low concentration of impurities.

4. The semiconductor device according to claim 3, wherein portions of the second conductive-type semiconductor region projecting into the first conductive-type semiconductor region are formed in such a manner as to contact the high-concentration impurity layer.

5. The semiconductor device according to claim 3, wherein portions of the second conductive-type semiconductor region projecting into the first conductive-type semiconductor region are formed in such a manner as to contact the high-concentration impurity layer and the low-concentration impurity layer.

6. The semiconductor device according to claim 4, wherein portions of the second conductive-type semiconductor regions projecting into the first conductive-type semiconductor region are formed in such a manner as to contact the high-concentration impurity layer and the low-concentration impurity layer.

7. A semiconductor device comprising:

a first conductive-type semiconductor region having a first surface and a second surface opposite to the first surface, and made from a first conductive-type semiconductor material in which carriers are injected from a channel formed of a gate electrode solely on the first surface; and

a second conductive-type semiconductor region made from a second conductive-type semiconductor material and formed in such a manner as to contact the second surface of the first conductive-type semiconductor region,

wherein an average interface of a contact surface between the first and second conductive-type semiconductor regions is formed in such a manner as to form a predetermined angle with the channel, and the contact surface is formed in a convexo-concave shape.

8. The semiconductor device according to claim 7, wherein the contact surface is at least partially formed as a curved surface.

9. The semiconductor device according to claim 7, wherein the first conductive-type semiconductor region has a high-concentration impurity layer demonstrating a high concentration of impurities and a low-concentration impurity layer formed on the high-concentration impurity layer and demonstrating a low concentration of impurities.

10. The semiconductor device according to claim 9, wherein portions of the second conductive-type semiconductor regions projecting into the first conductive-type semiconductor region are formed in such a manner as to contact the high-concentration impurity layer.

11. A method of manufacturing a trench-gate-type semiconductor device comprising a first conductive-type semiconductor region having a first surface and a second surface opposite to the first surface, and made from a first conductive-type semiconductor material into which carriers are injected from a channel formed of a gate electrode formed in a trench solely on the first surface and a second conductive-type semiconductor region made from a second conductive-type semiconductor material and formed in such a manner as to contact the second surface of the first conductive-type semiconductor region, comprising:

a semiconductor area forming process in which the first conductive-type semiconductor region and/or the second conductive-type semiconductor region are/is formed such that a contact surface between the first and second conductive-type semiconductor regions assumes a convexo-concave shape.

12. The method according to claim 11, wherein the semiconductor region forming process includes an impurity implantation process in which impurities are selectively implanted in the second conductive-type semiconductor regions and a diffusion process in which the first conductive-type semiconductor region is formed in such a manner as to contact the second conductive-type semiconductor regions and the impurities are diffused into the first conductive-type semiconductor region.

13. The method according to claim 11, wherein the semiconductor region forming process includes a groove forming process in which grooves are formed in the second conductive-type semiconductor regions and a process in which the first conductive-type semiconductor region is formed in such a manner as to contact the second conductive-type semiconductor regions.

14. The method according to claim 11, wherein the semiconductor region forming process includes a process in which the first conductive-type semiconductor region is formed and a process in which impurities in the second conductive-type semiconductor region are diffused into the first conductive-type semiconductor region to form the second conductive-type semiconductor region.