Dynamic input stage biasing for low quiescent current amplifiers

• US 6,509,722 B2
• Filed: 05/01/2001
• Issued: 01/21/2003
• Est. Priority Date: 05/01/2001
• Status: Expired due to Term

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Lopata, Douglas D.
• Primary Examiner(s): Nappi, Robert E.
• Assistant Examiner(s): Laxton, Gary L.
• Application Number:
  US09/846,844
• Publication Number:
  US 20020171403A1
• Time in Patent Office: 630 Days
• Field of Search: 323/265, 323/266, 323/268, 323/273-275, 323/277, 323/280, 323/311-314, 323/349, 323/350, 323/907, 330/270, 330/273, 330/285, 330/288, 330/290, 330/296, 330/129, 330/130
• US Class Current: 323/280
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: H03F 2203/45454 the CSC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45462 the CSC comprising a cascode circuit
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

An amplifier, for use in regulator circuits and other applications, having dynamic input stage biasing includes an input stage operatively coupled to an input of the amplifier. A controlled current source coupled to the input stage is responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source. The amplifier further includes a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source. The sense circuit measures an output load current from the amplifier and generates the control signal in response thereto, whereby the input bias current is a function of the output load current of the amplifier. In this manner, parasitic poles associated with the amplifier are pushed out in frequency so as to provide superior amplifier stability while dissipating low quiescent current, particularly at low output load current levels.

Claims

1. An amplifier having dynamic input stage biasing, the amplifier comprising:

an input stage operatively coupled to an input of the amplifier;

a controlled current source operatively coupled to the input stage, the controlled current source-being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

an output device operatively coupled to an output of the amplifier, the output device supplying an output load current at least when the amplifier is loaded which is responsive to an input signal presented to the output device; and

a sense circuit operatively connected in a feedback arrangement between the output device and the controlled current source, the sense circuit measuring at least a portion of the input signal presented to the output device and generating the control signal that is representative thereof;

whereby the input bias current is dynamically controlled as a function of the input signal presented to the output device.

5. The amplifier of claim 1, wherein:

the control signal is at least a portion of the output load current; and

the control signal is operatively summed with a current generated by the controlled current source.

7. The amplifier of claim 1, wherein the controlled current source comprises first and second transistors operatively coupled together in a cascode configuration, the first and second transistors forming a common cascode node that is coupled to the control input.

9. The amplifier of claim 1, wherein the amplifier is fabricated in an integrated circuit.

2. An amplifier having dynamic input stage biasing, the amplifier comprising:

a controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

an input stage comprising a differential pair including first and second active devices, each active device being operatively coupled to first and second inputs, respectively, of the amplifier, the active devices being operatively coupled to the controlled current source at a tail node; and

an input load operatively coupled to the differential pair; and

a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source, the sense circuit measuring an output load current from the amplifier and generating the control signal in response thereto;

whereby the input bias current is a function of the output load current of the amplifier.

3. The amplifier of claim 2, wherein the input load includes an input for receiving a second control signal for controlling a current flowing through the input load in response thereto, whereby the current flowing through the input load is a function of the output load current of the amplifier.

4. The amplifier of claim 2, wherein the differential pair comprises first and second NMOS transistors, each transistor having a gate terminal, a source terminal and a drain terminal, the source terminals of the first and second transistors being connected together and forming the tail node, the gate terminals of the first and second transistors forming the first and second inputs, respectively, of the amplifier, and the drain terminals of the first and second transistors being operatively coupled to the input load.

6. An amplifier having dynamic input stage biasing, the amplifier comprising:

an input stage operatively coupled to an input of the amplifier;

a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source, the sense circuit measuring an output load current from the amplifier and generating the control signal in response thereto; and

a second stage including a first input coupled to the input stage of the amplifier, a second input for receiving a second control signal, and an output coupled to the output of the amplifier, the second stage being responsive to the second control signal for controlling a current flowing through the second stage;

whereby the current flowing through the second stage and the input bias current are functions of the output load current of the amplifier.

8. An amplifier having dynamic input stage biasing, the amplifier comprising:

an input stage operatively coupled to an input of the amplifier;

a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source, wherein the controlled current source comprises first and second NMOS transistors, each transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal of the first transistor being connected to the input stage, the source terminal of the first transistor being connected to the drain terminal of the second transistor and to the control signal, the source terminal of the second transistor being connected to a current return of the amplifier, the gate terminals of the first and second transistors being coupled to first and second bias voltages, respectively; and

a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source, the sense circuit measuring an output load current from the amplifier and generating the control signal in response thereto;

whereby the input bias current is a function of the output load current of the amplifier.

10. A regulator circuit including an unregulated input and a regulated output and having dynamic input stage biasing, the regulator comprising:

an error amplifier including first and second inputs and an output, the error amplifier including an input stage operatively coupled to the first and second inputs of the error amplifier, and a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source, the error amplifier generating an error signal in response to a difference between a reference voltage coupled to the first input of the error amplifier and a measured voltage representing at least a portion of the regulated output of the regulator;

a pass device having a first terminal coupled to the unregulated input of the regulator, a second terminal coupled to the regulated output of the regulator, and a third terminal coupled to the output of the error amplifier, the pass device receiving the error signal and controlling a voltage drop between the first and second terminals of the pass device in response thereto;

a sense circuit operatively connected in a feedback configuration between the output of the regulator and the controlled current source in the error amplifier, the sense circuit measuring an output load current from the regulator and generating the control signal in response thereto;

whereby the input bias current of the error amplifier is a function of the output load current of the regulator.

11. The regulator of claim 10, wherein the input stage comprises:

a differential pair including first and second active devices, each active device being operatively coupled to the first and second inputs, respectively, of the error amplifier, the active devices being operatively coupled to the controlled current source at a tail node; and

an input load operatively coupled to the differential pair.

12. The regulator of claim 11, wherein:

the input load includes an input for receiving a second control signal for controlling a current flowing through the input load in response thereto;

whereby the current flowing through the input load is a function of the output load current of the regulator.

13. The regulator of claim 10, wherein the sense circuit comprises first and second PMOS transistors, each transistor having a gate terminal, a source terminal and a drain terminal, the gate terminals of the first and second transistors being coupled to the output of the error amplifier, the source terminal of the first transistor being connected to the unregulated input, the drain terminal of the first transistor being connected to the source terminal of the second transistor, and the drain terminal of the second transistor being operatively coupled to the controlled current source.

14. The regulator of claim 10, wherein:

the control signal is at least a portion of the output load current of the regulator; and

the control signal is operatively summed with a current generated by the controlled current source.

15. The regulator of claim 10, further comprising:

a second stage including a first input coupled to the input stage of the error amplifier, a second input for receiving a second control signal, and an output coupled to the output of the error amplifier, the second stage being responsive to the second control signal for controlling a current flowing through the second stage;

whereby the current flowing through the second stage is a function of the output load current of the regulator.

16. The regulator of claim 10, wherein the regulator is fabricated in an integrated circuit.

17. A method of reducing quiescent current of an amplifier, the method comprising the steps of:

sensing a signal presented to an output device associated with the amplifier, the output device supplying an output current from the amplifier, at least when the amplifier is loaded, which varies in response to the signal presented to the output device;

generating a control signal that is representative of at least a portion of the signal presented to the output device; and

controlling an input bias current flowing through an input stage of the amplifier in response to the control signal;

whereby the input bias current is dynamically controlled as a function of the signal presented to the output device.

18. The method of claim 17, wherein the step of controlling the input bias current of the amplifier comprises feeding back at least a portion of an output load current of the amplifier to the input stage.

19. The method of claim 17, further comprising the steps of:

dynamically controlling a bias current flowing through an input load operatively coupled to the input stage of the amplifier in response to the control signal.

20. The method of claim 17, further comprising the steps of:

dynamically controlling a bias current flowing through a second stage operatively coupled to the input stage of the amplifier in response to the control signal.

21. An integrated circuit including an amplifier comprising:

an input stage operatively coupled to an input of the amplifier;

a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

an output device operatively coupled to an output of the amplifier, the output device supplying an output load current, at least when the amplifier is loaded, which varies in response to an input signal presented to the output device; and

a sense circuit operatively connected in a feedback arrangement between the output device and the controlled current source, the sense circuit measuring at least a portion of the input signal presented to the output device and generating the control signal that is representative thereof;

whereby the input bias current is dynamically controlled as a function of the input signal presented to the output device.

22. The integrated circuit of claim 21, wherein the input stage comprises:

a differential pair including first and second active devices, each active device being operatively coupled to first and second inputs, respectively, of the amplifier, the active devices being operatively coupled to the controlled current source at a tail node; and

an input load operatively coupled to the differential pair.

23. An integrated circuit including an amplifier comprising:

a controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

an input stage comprising a differential pair including first and second active devices, each active device being operatively coupled to first and second inputs, respectively, of the amplifier, the active devices being operatively coupled to the controlled current source at a tail node; and

an input load operatively coupled to the differential pair; and

a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source, the sense circuit measuring an output load current from the amplifier and generating the control signal in response thereto;

wherein the input load includes an input for receiving a second control signal for controlling a current flowing through the input load in response thereto, whereby the current flowing through the input load and the input bias current are functions of the output load current of the amplifier.

24. An integrated circuit including an amplifier comprising:

an input stage operatively coupled to an input of the amplifier;

a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source;

a sense circuit operatively connected in a feedback arrangement between an output of the amplifier and the controlled current source, the sense circuit measuring an output load current from the amplifier and generating the control signal in response thereto; and

a second stage including a first input coupled to the input stage of the amplifier, a second input for receiving a second control signal, and an output coupled to the output of the amplifier, the second stage being responsive to the second control signal for controlling a current flowing through the second stage;

whereby the input bias current and the current flowing through the second stage are functions of the output load current of the amplifier.

25. An integrated circuit including an unregulated input and a regulated output, the integrated circuit comprising:

an error amplifier including first and second inputs and an output, the error amplifier comprising an input stage operatively coupled to the first and second inputs of the error amplifier, and a controlled current source operatively coupled to the input stage, the controlled current source being responsive to a control signal for at least partially controlling an input bias current generated by the controlled current source, the error amplifier generating an error signal in response to a difference between a reference voltage coupled to the first input of the error amplifier and a measured voltage representing at least a portion of the regulated output of the integrated circuit;

a pass device having a first terminal coupled to the unregulated input of the integrated circuit, a second terminal coupled to the regulated output of the integrated circuit, and a third terminal coupled to the output of the error amplifier, the pass device receiving the error signal and controlling a voltage drop between the first and second terminals of the pass device in response thereto;

a sense circuit operatively connected in a feedback configuration between the regulated output of the integrated circuit and the controlled current source in the error amplifier, the sense circuit measuring an output load current from the integrated circuit and generating the control signal in response thereto;

whereby the input bias current of the error amplifier is a function of the output load current of the integrated circuit.

26. The integrated circuit of claim 25, wherein the input stage comprises:

a differential pair including first and second active devices, each active device being operatively coupled to the first and second inputs, respectively, of the error amplifier, the active devices being operatively coupled to the controlled current source at a tail node; and

an input load operatively coupled to the differential pair.

27. The integrated circuit of claim 26, wherein:

the input load includes an input for receiving a second control signal for controlling a current flowing through the input load in response thereto;

whereby the current flowing through the input load is a function of the output load current of the integrated circuit.

28. The integrated circuit of claim 25, further comprising:

a second stage including a first input coupled to the input stage of the error amplifier, a second input for receiving a second control signal, and an output coupled to the output of the error amplifier, the second stage being responsive to the second control signal for controlling a current flowing through the second stage;

whereby the current flowing through the second stage is a function of the output load current of the integrated circuit.