Method and apparatus for reducing DC offset

• US 6,509,777 B2
• Filed: 01/23/2001
• Issued: 01/21/2003
• Est. Priority Date: 01/23/2001
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Resonext Communications, Inc. (Qorvo, Inc.)
• Inventors: Zhang, Pengfei, Razavi, Behzad
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/768,841
• Publication Number:
  US 20020097081A1
• Time in Patent Office: 728 Days
• Field of Search: 327/307, 327/316, 455/343, 455/3.02, 455/24, 375/316, 375/319
• US Class Current: 327/307
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.

Claims

1. A circuit comprising:

a signal path having an input terminal coupled to receive an input signal;

a variable gain circuit coupled to receive the input signal and to generate an output signal at an output terminal; and

an offset reduction circuit coupled to the output terminal, wherein, the offset reduction circuit comprises;

a variable gain transconductance amplifier;

a first capacitor coupled to the variable gain transconductance amplifier; and

a first switch coupled between the first capacitor and the output terminal,

wherein, a gain of the variable gain transconductance amplifier is adjusted in response to variations in a gain of the variable gain circuit.

2. The circuit of claim 1 wherein the variable gain transconductance amplifier comprises:

a first field effect transistor having a gate terminal coupled to the first capacitor, a first source/drain terminal coupled to the output terminal, and a second source/drain terminal coupled to a first current source device; and

a second field effect transistor having a gate terminal coupled to the first capacitor, a first source/drain terminal coupled to the output terminal, and a second source/drain terminal coupled to a second current source device via a programmable switch.

3. The circuit of claim 2 wherein the signal path is differential with the output terminal having a differential pair of wires, and wherein the first switch and the first and second transistors couple to a first one of the differential pair of wires.

4. The circuit of claim 3 wherein the offset reduction circuit further comprises:

a second capacitor coupled to the variable gain transconductance amplifier; and

a second switch coupled between the second capacitor and the second one of the differential pair of wires.

5. The circuit of claim 4 wherein the variable gain transconductance amplifier further comprises:

a third field effect transistor having a gate terminal coupled to the second capacitor, a first source/drain terminal coupled to a second one of the differential pair of wires, and a second source/drain terminal coupled to the first current source device; and

a fourth field effect transistor having a gate terminal coupled to the second capacitor, a first source/drain terminal coupled to the second one of the differential pair of wires, and a second source/drain terminal coupled to the second current source device via the programmable switch.

6. The circuit of claim 5 further comprising a pair of resistive loads respectively coupled to the differential pair of wires.

7. The circuit of claim 6 wherein the variable gain circuit comprises an input amplifier whose gain is programmably adjusted.

8. The circuit of claim 7 wherein the signal path further comprises a mixer having a first input coupled to an output of the input amplifier, a second input coupled to receive an oscillating signal, and a differential output coupled to the differential pair of wires.

9. The circuit of claim 1 wherein the offset reduction circuit further comprises a signal amplifier coupled between the output terminal and the variable gain transconductance amplifier.

10. The circuit of claim 9 wherein a gain of the signal amplifier is programmable.

11. A receiver circuit comprising:

an input amplifier coupled to receive an input radio frequency (RF) signal;

a mixer having one input coupled to an output of the input amplifier and a second input coupled to receive an oscillating signal, the mixer having a differential output with a pair of resistive load devices coupled to the differential output; and

an offset reduction circuit including;

a programmable transconductance amplifier having a differential output coupled to the differential output of the mixer,

a pair of switches respectively coupled between the differential output of the mixer and differential input of the programmable transconductance amplifier, and

a pair of capacitive elements respectively coupled to the pair of switches and the differential input of the programmable transconductance amplifier,

wherein, the programmable transconductance amplifier is configured such that its gain is programmably adjusted in response to changes in the gain of one of the input amplifier or the mixer.

12. The receiver circuit of claim 11 further comprising a voltage amplifier coupled between the differential output of the mixer and the pair of switches.

13. The receiver circuit of claim 11 further comprising:

a low pass filter coupled to the output of the mixer; and

an automatic gain control block coupled to an output of the low pass filter.

14. A transceiver comprising the receiver circuit of claim 11 coupled to a transmitter circuit.

15. An electronic system comprising the transceiver of claim 14 coupled to an interface bus, the electronic system being capable of wireless data communication with another electronic system via the transceiver.

16. The electronic system of claim 15 wherein the electronic system is a personal computer.

17. The electronic system of claim 16 wherein the personal computer further comprises a central processing unit (CPU), memory and I/O devices coupled to the interface bus.

20. The circuit of claim 11, wherein the differential output of the mixer comprises a first wire and second wire, and wherein the programmable transconductance amplifier comprises a first leg including:

a first field effect transistor having a gate terminal coupled to a first one of the pair of capacitive elements, a first source/drain terminal coupled to the first wire, and a second source/drain terminal coupled to a first current source device; and

a second field effect transistor having a gate terminal coupled to the first capacitor, a first source/drain terminal coupled to the first wire, and a second source/drain terminal coupled to a second current source device via a programmable switch.

21. The circuit of claim 20, wherein the programmable transconductance amplifier further comprises a second leg including:

a third field effect transistor having a gate terminal coupled to a second one of the pair of capacitive elements, a first source/drain terminal coupled to the second wire, and a second source/drain terminal coupled to the first current source device; and

a fourth field effect transistor having a gate terminal coupled to the second capacitor, a first source/drain terminal coupled to the second wire, and a second source/drain terminal coupled to the second current source device via the programmable switch.

22. The circuit of claim 12, wherein the voltage amplifier is a differential amplifier comprising first and second differential input n-channel transistors respectively coupled to first and second split-gate p-channel load transistors.

23. The receiver circuit of claim 11 wherein the programmable transconductance amplifier comprises a plurality of programmable transconductance elements, each programmable transconductance element comprising:

a pair of transistors having their gate terminals respectively coupled to the pair of switches, their first source/drain terminals respectively coupled to power supply via a respective load devices, and their second source/drain terminals coupled to a common node;

a switch transistor coupled between the common node and a bias node, with a gate terminal coupled to receive switch control signal; and

a bias transistor coupled between the bias node and ground. with a gate terminal coupled to receive a bias voltage.

24. The receiver circuit of claim 23 wherein the pair of switches and the pair of transistors comprise n-channel transistors.

25. The receiver of claim 24 wherein the capacitive elements comprise n-channel transistors configured to function as capacitors.

18. A method for reducing dc offset from a signal path in a receiver, comprising:

sampling the dc offset on the signal path at an output of a mixer;

storing the dc offset signal on a capacitive element;

feeding back the stored dc offset signal via a transconductance amplifier;

adjusting a gain of the transconductance amplifier in response to variations in signal gain along the signal path; and

subtracting the dc offset from the signal along the signal path.

19. The method of claim 18 further comprising amplifying a magnitude of a signal on the signal path before sampling and storing the dc offset.