Two transistor ferroelectric non-volatile memory

• US 6,510,073 B1
• Filed: 01/31/2002
• Issued: 01/21/2003
• Est. Priority Date: 01/31/2002
• Status: Expired due to Fees

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Lee, Jong-Jan, Hsu, Sheng Teng
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/062,850
• Time in Patent Office: 355 Days
• Field of Search: 365/145, 365/149, 257/295, 257/296
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A two transistor ferroelectric non-volatile memory cell includes a ferroelectric capacitor connected to a word line and having an upper electrode and a lower electrode; a first MOS transistor having a linear capacitor located at a gate oxide region thereof, wherein a gate of the first MOS transistor is connected to the lower electrode of said ferroelectric capacitor and wherein a drain of the first transistor is connected to a bit line; a second MOS transistor having a gate connected to a programming line, a drain connected to the lower electrode of the ferroelectric capacitor, and a source connected to a ground and the source of the first transistor; wherein, when a positive pulse is applied to the word line and to the programming line, a charge is placed on the ferroelectric capacitor and the ferroelectric capacitor is decoupled from the MOS linear capacitor by connecting the bottom electrode of the ferroelectric capacitor to the ground state. When a positive pulse is applied to the word line and a positive pulse is applied to the programming line, a “1” state is created. When a negative pulse is applied to the word line and a positive pulse is applied to the programming line, a “0” state is created.

Claims

1. A two transistor ferroelectric non-volatile memory comprising:

a ferroelectric capacitor connected to a word line and having an upper electrode and a lower electrode;

a first MOS transistor having gate connected to the lower electrode of said ferroelectric capacitor, wherein a drain of said first transistor is connected to a bit line, and wherein a source of said first MOS transistor is connected to a ground;

a MOS linear capacitor located at the gate oxide of said first MOS transistor; and

a second MOS transistor having a gate connected to a programming line, a drain connected to the lower electrode of said ferroelectric capacitor, and a source connected to a ground and said source of said first transistor.

2. The two transistor ferroelectric non-volatile memory of claim 1 wherein, when a positive pulse is applied to said word line and to said programming line, a charge is placed on said ferroelectric capacitor and said linear capacitor, and wherein, after the positive pulse is applied, said ferroelectric capacitor is decoupled from said linear MOS capacitor, thereby creating a “

1”

state in the memory.

3. The two transistor ferroelectric non-volatile memory of claim 1 wherein when a negative pulse is applied to the word line and a positive pulse is applied to the programming line, a “

0”

state is created.

4. The two transistor ferroelectric non-volatile memory of claim 1 wherein said first transistor is off on both “

1” and

“

0”

states, even when a voltage is applied to a bit line, thereby requiring a low standby current.

5. The two transistor ferroelectric non-volatile memory of claim 1 wherein, during a reading process of the memory in a “

1”

state, a positive pulse on the word line switches the ferroelectric domain and charges the linear capacitor.

6. The memory of claim 1 wherein, during a read-out cycle, the memory is read, and retains said charge on said ferroelectric capacitor.

7. A two transistor ferroelectric non-volatile memory comprising:

a ferroelectric capacitor connected to a word line and having an upper electrode and a lower electrode;

a first MOS transistor having gate connected to the lower electrode of said ferroelectric capacitor, wherein a drain of said first transistor is connected to a bit line, and wherein a source of said first MOS transistor is connected to a ground;

a MOS linear capacitor located at the gate oxide of said first MOS transistor;

a second MOS transistor having a gate connected to a programming line, a drain connected to the lower electrode of said ferroelectric capacitor, and a source connected to a ground and said source of said first transistor;

wherein, when a positive pulse is applied to said word line and to said programming line, a charge is placed on said ferroelectric capacitor and said ferroelectric capacitor is decoupled from said linear MOS capacitor, thereby creating a “

1”

state in the memory.

8. The two transistor ferroelectric non-volatile memory of claim 7 wherein when a negative pulse is applied to the word line and a positive pulse is applied to the programming line, a “

0”

state is created.

9. The two transistor ferroelectric non-volatile memory of claim 7 wherein said first transistor is off on both “

1” and

“

0”

states, even when a voltage is applied to a bit line, thereby requiring a low standby current.

10. The two transistor ferroelectric non-volatile memory of claim 7 wherein, during a reading process of the memory in a “

1”

state, a positive pulse on the word line switches the ferroelectric domain and charges the linear capacitor.

11. The two transistor ferroelectric non-volatile memory of claim 7 wherein, during a read-out cycle, the memory is read, and retains said charge on said ferroelectric capacitor.

12. A two transistor ferroelectric non-volatile memory comprising:

a ferroelectric capacitor connected to a word line and having an upper electrode and a lower electrode;

a first MOS transistor having gate connected to the lower electrode of said ferroelectric capacitor, wherein a drain of said first transistor is connected to a bit line, and wherein a source of said first MOS transistor is connected to a ground;

a MOS linear capacitor located at the gate oxide of said first MOS transistor; and

a second MOS transistor having a gate connected to a programming line, a drain connected to the lower electrode of said ferroelectric capacitor, and a source connected to a ground and said source of said first transistor;

wherein when a negative pulse is applied to the word line and a positive pulse is applied to the programming line, a “

0”

state is created.

13. The two transistor ferroelectric non-volatile memory of claim 12 wherein, when a positive pulse is applied to said word line and to said programming line, a charge is placed on said ferroelectric capacitor and said linear capacitor, and wherein, after the positive pulse is applied, said ferroelectric capacitor is decoupled from said linear MOS capacitor, thereby creating a “

1”

state in the memory.

14. The two transistor ferroelectric non-volatile memory of claim 12 wherein said first transistor is off on both “

1” and

“

0”

states, even when a voltage is applied to a bit line, thereby requiring a low standby current.

15. The two transistor ferroelectric non-volatile memory of claim 12 wherein, during a reading process of the memory in a “

1”

state, a positive pulse on the word line switches the ferroelectric domain and charges the linear capacitor.

16. The two transistor ferroelectric non-volatile memory of claim 12 wherein, during a read-out cycle, the memory is read, and retains said charge on said ferroelectric capacitor.