Method and apparatus for transferring data in a dual port memory

• US 6,510,098 B1
• Filed: 05/28/1997
• Issued: 01/21/2003
• Est. Priority Date: 05/28/1997
• Status: Expired due to Fees

• Current Assignee: Foothills IP LLC
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Taylor, Ronald T.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US08/864,506
• Time in Patent Office: 2,064 Days
• Field of Search: 365/230.05, 365/189.04, 365/230.01, 365/230.06, 365/230.03
• US Class Current: 365/230.05
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory system 20 includes a first array 100 and a second array 102 of memory cells. The memory system allows for a quick transfer of the contents of one of the arrays with another one of the arrays. Through the use of a transfer gate (128) interposed between column decoders (150 and 152) corresponding to the two memory arrays, data may be transferred between the two arrays in a single timing cycle. Furthermore, even given the interconnection between the two memory arrays due to the transfer gate, the two memory arrays can be operated independently of one another, with respect to address, data, and timing information.

Claims

1. A memory system, comprising:

a first array of memory cells having a first plurality of rows and a first plurality of columns, wherein a first one of the first plurality of rows corresponds to a first predetermined wordline and a first one of the first plurality of columns corresponds to a first predetermined bit line;

a second array of memory cells having a second plurality of rows and a second plurality of columns, wherein a first one of the second plurality of rows corresponds to a second predetermined wordline and a first one of the second plurality of columns corresponds to a second predetermined bit line;

first control circuitry for receiving a first plurality of address bits and a first plurality of control signals for independently accessing said first array;

second control circuitry for receiving a second plurality of address bits and a second plurality of control signals for independently accessing said second array;

a first column decoder coupled to the first bit line of the first array to selectively access the first array of memory cells;

a second column decoder coupled to the second bit line of the second array to selectively access the second array of memory cells;

a transfer gate having a first terminal coupled to the first predetermined bit line, a second terminal coupled to the second predetermined bit line, and a third terminal coupled to a source of the transfer control signal, the transfer gate selectively transferring a first data accessed by the first column decoder to the second column decoder and selectively transferring a second data accessed by the second column decoder to the first column decoder in response to a logic state of the transfer control signal.

2. The memory system of claim 1 wherein the first data is transferred to a first selected memory cell in the second array when the first data is transferred-to the second column decoder.

3. The memory system of claim 1 wherein the second data is transferred to a first selected memory cell in the first array when the second data is transferred to the first column decoder.

4. A method for operating a memory system having a first array of memory cells and a second array of memory cells, the first array associated with a first port and a first column decoder and the second array associated with a second port and a second column decoder, comprising the steps of:

independently exchanging a first data between the first port and the first column decoder and the first array of memory cells;

independently exchanging a second data between the second port and the second column decoder and the second array of memory cells;

selectively enabling a transfer circuit to transfer the first data from the first column decoder to the second column decoder; and

selectively enabling the transfer circuit to transfer the second data from the second column decoder to the first column decoder.

5. The method of claim 4 wherein the first array of memory cells comprises a first plurality of bit lines and wherein the second array of memory cells comprises a second plurality of bit lines.

6. The method of claim 5, further comprising the steps of:

coupling the first plurality of bit lines to the first column decoder; and

coupling the second plurality of bit lines to the second column decoder.

7. The method of claim 6, further comprising the step of:

selectively coupling each of the first plurality of bit lines with a preselected one of the second plurality of bit lines.

8. The method of claim 7 wherein the transfer circuit comprises a plurality of transistors for selectively coupling each of the first plurality of bit lines with the preselected one of the second plurality of bit lines.

9. The method of claim 4, further comprising the step of:

transferring the first data from the first column decoder to the second array when the first data are communicated with the first array before the second plurality of data are communicated with the second array.

10. The method of claim 4, further comprising the step of:

transferring the second data from the second column decoder to the first array when the second data are communicated with the second array before the first plurality of data are communicated with the first array.