Processing semiconductor devices having some defective input-output pins

• US 6,510,443 B1
• Filed: 12/07/1998
• Issued: 01/21/2003
• Est. Priority Date: 12/07/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Prak, Sovandy, Charlton, David
• Primary Examiner(s): WACHSMAN, HAL D
• Application Number:
  US09/207,090
• Time in Patent Office: 1,506 Days
• Field of Search: 702/118, 702/33-35, 702/38, 702/40, 702/57-59, 702/64, 702/65, 702/81-84, 702/117, 702/108, 702/119-123, 702/170, 702/172, 702/182-185, 702/FOR.170, 702/FOR.171, 702/FOR-103, 702/FOR-123, 702/FOR.131, 702/FOR.134, 702/FOR.135, 702/FOR.137, 702/FOR.138, 700/109, 700/110, 700/115-121, 365/201, 438/5, 438/7, 438/10-12, 438/14, 438/16-18, 382/141, 382/144-146, 382/149, 209/571-574, 324/73.1, 324/764, 324/765, 324/555, 324/761, 324/158.1
• US Class Current: 702/118
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/886 combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device

Abstract

Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.

Claims

1. A method to process partially defective semiconductor memory devices, comprising:

testing a plurality of semiconductor memory devices, each semiconductor memory device having a plurality of input-output pins;

identifying an operational state of each of the plurality of input-output pins for each of the plurality of semiconductor memory devices;

generating a code indicating the operational state of each of the plurality of input-output pins for each of the plurality of semiconductor memory devices; and

associating each generated code with an identifier of the semiconductor memory device tested to generate the code.

2. The method of claim 1, further comprising:

identifying a target operational state of a target device;

identifying a first semiconductor memory device having a first code; and

identifying a second semiconductor memory device having a second code, based on the target operational state, the first code, and the second code.

3. The method of claim 2, wherein the act of identifying a target operational state comprises specifying a number of operational input-output pins.

4. The method of claim 3, wherein the act of identifying a second semiconductor memory device comprises selecting the second semiconductor memory device if the sum of the number of operational input-output pins of the first semiconductor memory device indicated by the first code and the number of operational input-output pins of the second semiconductor memory device indicated by the second code is greater than or equal to the target operational state.

5. The method of claim 2, further comprising combining the first semiconductor memory device and the second semiconductor memory device to form a component.

6. The method of claim 5, wherein the act of combining the first semiconductor memory device and the second semiconductor memory device comprises forming the component having two or more semiconductor memory devices, the component adapted to function as a single, fully operational, semiconductor memory device.

7. The method of claim 1, wherein the act of testing a plurality of semiconductor memory devices comprises determining a number of operational input-output pins for each of the plurality of semiconductor memory devices.

8. The method of claim 1, wherein the act of generating a code comprises generating a hexadecimal code indicating which input-output pins are operational.

9. The method of claim 1, wherein the act of associating each generated code with an identifier of the semiconductor memory device tested comprises storing the code and the unique identifier in a database record.

10. The method of claim 1, further comprising performing an additional test on at least operational input-output pins of each semiconductor memory device.

11. The method of claim 10, further comprising updating the generated code for each semiconductor memory device if the additional test indicates further defective one or more input-output pins.

12. The method of claim 10, wherein performing the additional test comprises performing at least one of a device speed test, pin-to-pin current test, current drain measurement, voltage-on low and high test, and noise immunity test.

13. The method of claim 1, further comprising disabling in-operative one or more input-output pins based on the generated code.

14. A system for testing devices, each device having plural pins, the system comprising:

a storage module; and

a control module adapted to test the devices and to store a code identifying an operational state of pins of each of the devices in the storage module,

the control module adapted to further associate each code with an identifier of a corresponding device.

15. The system of claim 14, wherein the identifier comprises one or more of a lot identification number, process tray identification number, device location, and device identification.