Method and apparatus for high-speed network rule processing

• US 6,510,509 B1
• Filed: 03/29/1999
• Issued: 01/21/2003
• Est. Priority Date: 03/29/1999
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Iyer, Sundar, Yadav, Navneet, Chopra, Vikram, Desai, Ajay, Jiandani, Moti, Shelat, Ajit, Iyer, Raghunath
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/280,235
• Time in Patent Office: 1,394 Days
• Field of Search: 712/13, 719/236, 719/238
• US Class Current: 712/13
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.

Claims

1. A method of quickly processing an incoming packet, said method comprising:

distributing information from said incoming packets from a main control unit to a plurality of nanocomputers, said nanocomputers organized into groups, each of said nanocomputers comprising a set of instructions;

concurrently processing said incoming packets within said nanocomputers using at least one instruction in said nanocomputers to generate an instruction outcome in each said nanocomputer;

determining a group prioritized result within each nanocomputer group;

determining a global prioritized result from said group prioritized result; and

returning a prioritized final result to said main control unit, said prioritized final result comprising a highest priority instruction outcome from said plurality of nanocomputers.

2. The method as claimed in claim 1 further comprising:

returning a prioritized final result to said main control unit, said prioritized final result comprising a highest priority instruction outcome from said plurality of nanocomputers.

3. The method as claimed in claim 1 wherein said groups of nanocomputers her comprise a group control unit.

4. The method as claimed in claim 3 wherein adjacent nanocomputers in a nanocomputers group may be linked such that instructions in adjacent nanocomputers may be treated as a single instruction.

5. The method as claimed in claim 3 wherein said group control unit determines said group prioritized result.

6. The method as claimed in claim 5 wherein said group control unit determines said group prioritized result by polling nanocomputers in said group of nanocomputers.

7. The method as claimed in claim 1 wherein each nanocomputer comprises an arithmetic logic unit.

8. The method as claimed in claim 1 wherein each nanocomputer comprises am memory.