Digital signal processor having distributed register file
First Claim
1. A computation block for performing digital signal computations, comprising:
- a register file for storage of operands and results of said digital signal computations;
first and second computation units for executing said digital signal computations using said operands and producing said results;
one or more operand buses each coupled between an operand output of said register file and an operand input of said first and second computation units; and
one or more result buses each coupled to a result output of said first and second computation units, to an intermediate result input of said first and second computation units and to a result input of said register file, wherein an intermediate result of a digital signal computation may be transferred directly from the result output of one of said computation units to the intermediate result inputs of one or both of said first and second computation units for use in a subsequent computation without first transferring the intermediate result to said register file, wherein each of said computation units comprises a first latch having inputs coupled to each of said operand buses and each of said result buses, a first multiplexer having inputs coupled to said first latch for selecting a first operand from one of said operand buses or one of said result buses in response to a first control signal, a second latch having inputs coupled to each of said operand buses and each said result buses, a second multiplexer having inputs coupled to said second latch for selecting a second operand from one of said operand buses or one of said result buses in response to a second control signal, a computation circuit for receiving said first and second operands and executing said digital signal computation, and an output latch having an input coupled to said computation circuit and an output coupled to one or more of said result buses.
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Abstract
A computation block for use in a digital signal processor includes a register file for storage of operands and results and one or more computation units for executing digital signal computations. A first digital signal computation is performed with one of the computation units, and an intermediate result is produced. The intermediate result is transferred from a result output of the computation unit to an intermediate result input of one or more of the computation units without first transferring the intermediate result to the register file. A second digital signal computation is performed using the intermediate result to produce a final result or a second intermediate result.
95 Citations
17 Claims
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1. A computation block for performing digital signal computations, comprising:
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a register file for storage of operands and results of said digital signal computations;
first and second computation units for executing said digital signal computations using said operands and producing said results;
one or more operand buses each coupled between an operand output of said register file and an operand input of said first and second computation units; and
one or more result buses each coupled to a result output of said first and second computation units, to an intermediate result input of said first and second computation units and to a result input of said register file, wherein an intermediate result of a digital signal computation may be transferred directly from the result output of one of said computation units to the intermediate result inputs of one or both of said first and second computation units for use in a subsequent computation without first transferring the intermediate result to said register file, wherein each of said computation units comprises a first latch having inputs coupled to each of said operand buses and each of said result buses, a first multiplexer having inputs coupled to said first latch for selecting a first operand from one of said operand buses or one of said result buses in response to a first control signal, a second latch having inputs coupled to each of said operand buses and each said result buses, a second multiplexer having inputs coupled to said second latch for selecting a second operand from one of said operand buses or one of said result buses in response to a second control signal, a computation circuit for receiving said first and second operands and executing said digital signal computation, and an output latch having an input coupled to said computation circuit and an output coupled to one or more of said result buses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computation block for performing digital signal computations, comprising:
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a register file for storage of operands and results of said digital signal computations, said register file having an operand output and a result input;
at least one computation unit for executing said digital signal computations using said operands and producing said results, said computation unit having an operand input, an intermediate result input and a result output;
at least one operand bus coupled between the operand output of said register file and the operand input of said computation unit; and
at least one result bus coupled to the result output of said computation unit, to the intermediate result input of said computation unit and to the result input of said register file, wherein an intermediate result of a digital signal computation may be transferred directly from the result output of said computation unit to the intermediate result input of said computation unit for use in a subsequent computation without first transferring the intermediate result to said register file, wherein said computation unit comprises a first latch coupled to said operand bus and said result bus, a first multiplexer having inputs coupled to said first latch for selecting a first operand from said operand bus or said result bus in response to a first control signal, a second latch having inputs coupled to said operand bus and said result bus, a second multiplexer having inputs coupled to said second latch for selecting a second operand from said operand bus or said result bus in response to a second control signal, a computation circuit receiving said first and second operands from said first and second multiplexers, respectively, and an output latch having an input coupled to said computation circuit and having an output coupled to said result bus. - View Dependent Claims (11, 12)
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13. A computation unit for performing digital signal computations, comprising:
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a computation circuit having a first input for receiving a first operand used in digital signal computations and a second input for receiving a second operand used in digital signal computations;
a first operand latch having an input coupled to at least one operand bus for storing operands passed on the at least one operand bus from an external register file;
a first intermediate result latch having an input coupled to at least one result bus for storing operands from the at least one result bus;
a second operand latch having an input to coupled to the at least one operand bus for storing operands passed on the at least one operand bus from the external register file;
a second intermediate result latch having an input coupled to the at least one result bus for storing operands from the at least one result bus;
a first multiplexer for selecting a first operand from one of the first operand latch and first intermediate result latch and supplying the first operand to the first input of the computation circuit; and
a second multiplexer for selecting a second operand from one of the second operand latch and second intermediate result latch and supplying the second operand to the second input of the computation circuit. - View Dependent Claims (14, 15, 16, 17)
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Specification