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Method for detecting or repairing intercell defects in more than one array of a memory device

  • US 6,510,533 B1
  • Filed: 12/26/2000
  • Issued: 01/21/2003
  • Est. Priority Date: 03/24/1998
  • Status: Expired due to Term
First Claim
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1. A method of establishing digit line voltages in a memory device having a plurality of memory arrays, comprising:

  • applying voltages to a first set of memory cells in a first of the arrays;

    producing sense amplifier voltages by coupling respective sense amplifiers to memory cells in the first set through respective pairs of complimentary digit lines; and

    using the sense amplifiers that produced the sense amplifier voltages to apply the produced sense amplifier voltages to memory cells in a second of the arrays through respective pairs of complimentary digit lines.

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