IC-compatible parylene MEMS technology and its application in integrated sensors

• US 6,511,859 B1
• Filed: 03/10/2000
• Issued: 01/28/2003
• Est. Priority Date: 03/12/1999
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Wang, Xuan-Qi, Han, Zhigang, Tai, Yu-Chong, Jiang, Fukang
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Keshavan, Belur V.
• Application Number:
  US09/523,399
• Time in Patent Office: 1,054 Days
• Field of Search: 438/24, 438/48, 438/50, 438/52, 438/53, 438/691, 438/619, 438/635, 438/702, 438/106, 438/108, 438/114, 216/79, 156/643, 257/419
• US Class Current: 438/48
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit

Abstract

A combined IC/Mems process forms the IC parts first, and then forms the MEMS parts. One option forms a parylene overlayer, then forms a cavity under the parylene overlayer.

Claims

1. A method of forming a structure, comprising:

obtaining a semiconductor structure on a semiconductor substrate with multiple semiconductor layers;

forming a structural portion over the semiconductor structures, said structural portion including parylene; and

etching an opening which leaves said parylene structure and semiconductor structure intact and unsupported by other structural elements other than said parylene structure and said semiconductor substrate.

2. The method of claim 1 wherein said etching an opening comprises etching a hole under the structure using bromine trifluoride etching.

3. The method as in claim 1, wherein said etching an opening comprises forming a sacrificial layer, and removing said sacrificial layer.

4. The method of claim 3, wherein said sacrificial layer includes photoresist.

5. The method of claim 3, wherein said sacrificial layer includes amorphous silicon.

6. The method of claim 1, wherein said parylene is poly-para-xylylene.

7. The method of claim 1, wherein said etching uses a gas phase etchant.

8. A method of forming a structure, comprising:

first forming a semiconductor structure on a substrate;

after forming said semiconductor structure, forming a parylene structural element, coupled to at least part of said semiconductor structure, and physically supporting said semiconductor structure; and

etching away said substrate in at least one location so that said semiconductor structure is supported only by said parylene.

9. The method of claim 8, wherein said semiconductor structure includes a dielectric portion formed of parylene.

10. The method of claim 8, wherein said parylene structural element supports a wall of a cavity.

11. The method of claim 8, wherein said parylene is used along with photoresist.

12. The method of claim 8, further comprising etching using a gas phase etchant.

13. The method of claim 12, wherein said gas phase etchant is gas phase bromine trifluoride used as a isotropic silicon etchant, used to form a cavity under the parylene layer.

14. A device, comprising:

an electrical structure including a biasing circuit, amplifying circuit, and at least one other circuits formed using an integrated circuit process, on a semiconductor substrate;

a polysilicon gate, associated with said electrical structure; and

a parylene structural element, associated with said electrical structure, and covering an opening below the electrical structure and supports the electrical structure relative to the opening.