Semiconductor device with Si-Ge layer-containing low resistance, tunable contact

• US 6,511,905 B1
• Filed: 01/04/2002
• Issued: 01/28/2003
• Est. Priority Date: 01/04/2002
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Walsh, John, Lee, Brian S.
• Primary Examiner(s): Booth, Richard
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US10/035,221
• Time in Patent Office: 389 Days
• Field of Search: 438/627, 438/628, 438/629, 438/643, 438/644, 438/648, 438/653, 438/654, 438/656, 438/657, 438/659
• US Class Current: 438/629
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76859 by ion implantation
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects

Abstract

The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si_xGe_1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Claims

1. A process for fabricating a metal contact at a metal/semiconductor interface, comprising the following steps:

forming a dielectric layer on a semiconductor substrate;

forming a contact opening in the dielectric layer to expose the semiconductor substrate;

forming a Si_xGe<sub>1−

x</sub> layer in the contact opening, wherein 0<

x<

1; and

filling a metal plug over the Si_xGe<sub>1−

x</sub> layer into the contact opening.

2. The process as claimed in claim 1, wherein the Si_xGe₁₋

x layer is formed by selective epitaxial growth.

3. The process as claimed in claim 1, wherein the metal plug is a tungsten plug formed by selective tungsten deposition.

4. The process as claimed in claim 1 wherein the Si_xGe₁₋

x layer is a silicon-rich Si_xGe<sub>1−

x</sub> layer and 0.5<

x<

0.95.

6. The process as claimed in claim 1, wherein the Si_xGe₁₋

x layer has a thickness greater than or equal to 5 nm and less than or equal to 30 nm.

7. The process as claimed in claim 1, further comprising, after the Si_xGe₁₋

x layer is formed and before the metal plug is filled, the following step;

forming a metal silicide layer on the Si_xGe<sub>1−

x</sub> layer layer.

8. The process as claimed in claim 7, wherein the Si_xGe₁₋

x layer has a thickness more than 30 nm.

9. The process as claimed in claim 1, further comprising, after the Si_xGe₁₋

x layer is formed and before the metal plug is filled, the following step;

forming a glue layer and a diffusion barrier layer both on the Si_xGe<sub>1−

x</sub> layer and on the sides of the contact opening.

5. The process as claimed in claim l, wherein the Si_xGe₁₋

x layer is a strained Si_xGe<sub>1−

x</sub> layer not causing dislocation in the semiconductor substrate.

10. A process for fabricating a metal contact at a metal/semiconductor interface, comprising the following steps:

forming a dielectric layer on a semiconductor substrate;

forming a contact opening in the dielectric layer to expose the semiconductor substrate;

forming a Si_xGe<sub>1−

x</sub> layer in the contact opening, wherein 0<

x<

1;

forming a metal layer on the Si_xGe<sub>1−

x</sub> layer;

implanting a dopant into the metal layer and the Si_xGe<sub>1−

x</sub> layer;

conducting annealing to transform the metal layer into a metal silicide layer and to diffuse the dopant into the semiconductor substrate to form a diffusion region; and

filling a metal plug over the Si_xGe<sub>1−

x</sub> layer into the contact opening.

11. The process as claimed in claim 10, wherein the implanting is conducted at a high energy and low dose,

wherein the high energy is 20 KeV to 80 KeV and the low dose is 1E14 atoms/cm² to 1E15 atoms/cm².

12. The process as claimed in claim 10, wherein the implanting is conducted by an ion mixing method including a first implantation at a low energy and high dose, and a second implantation at a high energy and low dose,

wherein the low energy is 100 eV to 10 KeV and the high dose is 1×

10¹⁵ to 1×

10¹⁶ atoms/cm², the high energy is 20 KeV to 80 KeV and the low dose is 5E13 to 5E14 atoms/cm².

13. The process as claimed in claim 10, wherein the step of forming a metal layer includes forming a glue layer and a diffusion barrier layer both on the Si_xGe₁₋

x layer and on the sides of the contact opening.

14. A process for fabricating a metal contact at a metal/semiconductor interface, comprising the following steps:

forming a dielectric layer on a semiconductor substrate;

forming a contact opening in the dielectric layer to expose the semiconductor substrate;

forming a Si_xGe<sub>1−

x</sub> layer in the contact opening, wherein 0<

x<

1;

forming a consumable polysilicon layer on the Si_xGe<sub>1−

x</sub> layer in the contact opening; and

filling a metal plug over the Si_xGe<sub>1−

x</sub> layer into the contact opening.

15. The process as claimed in claim 14, further comprising, after the consumable polysilicon layer is formed and before the metal plug is filled, the following steps:

forming a metal layer on the consumable polysilicon layer;

implanting a dopant into the metal layer, polysilicon layer, and the Si_xGe<sub>1−

x</sub> layer; and

conducting annealing to transform the metal layer into a metal silicide layer and to diffuse the dopant into the semiconductor substrate in a SADS (salicide as a doping source) manner to form a diffusion region.

16. The process as claimed in claim 15, wherein the step of forming a metal layer includes forming a glue layer and a diffusion barrier layer both on the consumable polysilicon layer and on the sides of the contact opening.

17. The process as claimed in claim 14, wherein the step of forming the consumable polysilicon layer includes conformally forming the consumable polysilicon layer both on the Si_xGe₁₋

x layer and on the sides of the contact opening.

18. The process as claimed in claim 14, wherein the consumable polysilicon layer has a thickness of 10 nm to 50 nm.