Method of fabricating semiconductor device

• US 6,512,265 B2
• Filed: 03/27/2002
• Issued: 01/28/2003
• Est. Priority Date: 08/28/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Imai, Yasuo, Ohnishi, Akihiro, Numazawa, Sumito, Kubo, Sakae
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): KESHAVAN, BELUR V
• Application Number:
  US10/106,364
• Publication Number:
  US 20020098656A1
• Time in Patent Office: 307 Days
• Field of Search: 257/330, 257/341, 257/342, 257/328, 257/288, 438/270, 438/212, 438/268, 438/327, 438/342
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A semiconductor device having a MISFETs forming region and a gate lead-out region in a semiconductor substrate, comprising:

a plurality of trenches in said semiconductor substrate in said MISFETs forming region,

a plurality of gate oxide films of said MISFETs formed in said plurality of trenches,

a plurality of gate electrodes of said MISFETs formed on said plurality of gate oxide films,

a first conductive film formed over said semiconductor substrate in said gate lead-out region,

wherein the top surface of said gate electrodes is lower than the top surface of said semiconductor substrate in said gate lead-out region,

wherein said plurality of gate electrodes are electrically connected with said first conductive film.

2. A semiconductor device according to claim 1, wherein said plurality of gate electrodes are disposed in parallel.

3. A semiconductor device according to claim 1, wherein said plurality of gate electrodes are electrically connected.

4. A semiconductor device according to claim 1, wherein said gate electrodes and first conductive film are comprised of polycrystalline silicon.

5. A semiconductor device according to claim 1, further comprising:

a first insulation film formed over said first conductive film,

a second conductive film formed over said first insulation film,

wherein said first and second conductive films are electrically connected.