High-voltage high-speed SOI MOSFET

• US 6,512,269 B1
• Filed: 09/07/2000
• Issued: 01/28/2003
• Est. Priority Date: 09/07/2000
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward Joseph, Tong, Minh Ho, Bryant, Andres
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/657,315
• Time in Patent Office: 873 Days
• Field of Search: 257/347, 257/350, 257/351, 257/365, 257/401
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device including an SOI substrate; a plurality of diffusion regions in substrate, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.

Claims

1. An silicon-on-insulator semiconductor device comprising:

an silicon-on-insulator substrate including at least an active region disposed on an electrically insulating region;

a plurality of diffusion regions in said active region, separated by, and abutting a plurality of body regions in said substrate, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and

a plurality of gate conductors each over one of the plurality of body regions and separated from the body regions by a dielectric material, wherein said plurality of gate conductors and said dielectric have an aspect ratio in terms of gate conductor length to dielectric material thickness of from about 10;

1 to about 30;

1, and wherein said silicon-on-insulator semiconductor device has a drain-to-source breakdown voltage of at least approximately 2.5V.

2. The silicon-on-insulator semiconductor device of claim 1 wherein a diffusion region at a first end has a drain terminal and a diffusion region at a second end has a source terminal.

3. The silicon-on-insulator semiconductor device of claim 1 further comprising diffusion regions between gate conductor that extend vertically through the entire active region of the substrate.

4. The silicon-on-insulator semiconductor device of claim 1 wherein said plurality of gate conductors are each disposed on respective said dielectric material.

5. The SOI semiconductor device of claim 4 wherein each of said gate conductors is a conductive material selected from the group consisting of polysilicon, elemental metals and nitrides of elemental metals.

6. The SOI semiconductor device of claim 5 wherein said gate conductor is composed of polysilicon.

7. The silicon-on-insulator semiconductor device of claim 1 wherein said plurality of gate conductor each include sidewall spacers thereon.

8. The SOI semiconductor device of claim 7 wherein said sidewall spacers are composed of SiO₂ or Si₃N₄.

9. The silicon-on-insulator semiconductor device of claim 1 wherein said dielectric material is a thick dielectric having a thickness of from about 20 to about 100 Å

.

10. The silicon-on-insulator semiconductor device of claim 1 wherein said dielectric is selected from the group consisting of oxides, nitrides, oxynitrides, Al₂O₃, ZrO₂ and mixtures or multilayers thereof.

11. The silicon-on-insulator semiconductor device of claim 1 wherein said plurality of gate conductor each have a gate length of from about 30 to about 300 nm.

12. The SOI semiconductor device of claim 1, wherein said device has a first end and a second end, and wherein

a first one of said plurality of diffusion regions at said first end has a first depth; and

a second one of said plurality of diffusion regions at said second end has a second depth different from said first depth.