Method for testing semiconductor devices

• US 6,512,392 B2
• Filed: 12/15/2000
• Issued: 01/28/2003
• Est. Priority Date: 04/17/1998
• Status: Expired due to Fees

• Current Assignee: Kyoei Sangyo Company Limited, Mitsubishi Electric Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Patrick, Jon A., Fleury, Roger W.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/738,553
• Publication Number:
  US 20010000649A1
• Time in Patent Office: 774 Days
• Field of Search: 324/760, 324/765, 324/763, 165/80.3, 165/80.4, 438/14, 438/17-18, 257/40, 257/48, 714/724, 714/730-735
• US Class Current: 324/762.03
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits

Abstract

Method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effetively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices.

Claims

1. A method for testing integrated circuit semiconductor device comprising the steps of;

a) providing a wafer containing a plurality of integrated semiconductor devices having short and long gate width;

b) determining functionality of said integrated semiconductor devices at a predetermined set of operating conditions;

c) segregating said integrated semiconductor devices on said wafer by measuring operating speed of said devices by determining which of said devices on said wafer have short gate channel widths;

d) applying a stress test to said devices wherein test conditions of said stress test are adjusted based on said segregation parameter measurements of said devices;

e) determining functionality of said devices at nominal operating conditions after said stress test; and

,

f) classifying said devices as failed if said dices do not function properly after said stress test.

2. The method of claim 1 wherein the step of measuring the operational speed of said devices comprises using flush delay time measurements or a performance sort ring oscillator to determine said operational speed of said devices.

3. The method of claim 1, further comprising the steps of assigning supply current specification limits and measuring said limits for said devices, such that, a first supply current specification limit is assigned to devices with a faster of said operational speeds and a second supply current specification limit is assigned to devices with a slower of said operational speeds, said first supply current limit being greater than said second supply current limit.

4. A method for testing integrated circuit semiconductor devices comprising the steps of;

a) providing a wafer containing a plurality of integrated semiconductor devices;

b) determining functionality of said integrated semiconductor devices at a predetermined set of operating conditions;

c) segregating said integrated semiconductor devices on said wafer by measuring operating speed of said devices;

d) applying a stress test to said devices wherein test conditions of said stress test are adjusted based on said segregation parameter measurements of said devices by applying a first voltage at a value higher than the device normal operating voltage to said devices with a first measured operational speed, and a second voltage at a value lower than said first voltage to said devices with a second measured operational speed, said fast operational speed being less than said second operational speed;

e) determining functionality of said devices at nominal operating conditions after said stress test; and

,

f) classifying said devices as failed if said devices do not function properly after said stress test.

5. A method for testing integrated circuit semiconductor devices comprising the steps of:

a) providing a wafer containing a plurality of integrated semiconductor devices which includes n-type and p-type field effect transistors;

b) determining functionality of said integrated semiconductor devices at a predetermined set of operating conditions;

c) segregating said integrated semiconductor devices on said wafer by measuring operating speed of said devices comprises the steps of;

i) measuring drain-to-source current for said n-type and p-type field effect transistors;

ii) determining a drain-to-source current sum by summing the value of said n-type drain-to-source current with the absolute value of said p-type drain-to-source current;

iii) determining a device ISUM value by dividing said drain-to-source current sum by said gate channel width of said device; and

iv) segregating said devices based on said ISUM value wherein said devices with lower ISUM values correspond to slower operational speeds and devices with higher ISUM values correspond to faster operation speeds;

d) applying a stress test to said devices wherein test conditions of said stress test are adjusted based on said segregation parameter measurement of said devices;

e) determining functionality of said devices at nominal operating conditions after said stress test; and

,

f) classifying said devices as failed if said dices do not function properly after said stress test.

6. The method of claim 5, wherein said step (iv), segregating said devices based on said ISUM value, further comprises assigning devices with ISUM values less than or equal to 700 μ

a/μ

m as slower operational speed devices.