Configurable memory for programmable logic circuits
First Claim
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1. An apparatus comprising:
- a memory device configured to;
receive one or more inputs from a first bus and a second bus;
present one or more outputs to said first bus and said second bus; and
operate in one or more modes in response to information stored in a programmable logic circuit.
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Abstract
An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
87 Citations
18 Claims
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1. An apparatus comprising:
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a memory device configured to;
receive one or more inputs from a first bus and a second bus;
present one or more outputs to said first bus and said second bus; and
operate in one or more modes in response to information stored in a programmable logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
said programmable logic device comprises a first routing channel run parallel to a first axis and a second routing channel run parallel to a second axis; and
said memory device is connected to said first routing channel and to said second routing channel.
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17. A memory device comprising:
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means for receiving one or more inputs from a first bus and a second bus;
means for presenting one or more outputs to said first bus and said second bus;
means for operating in one or more modes in response to one or more control signals; and
means for programmably generating said control signals.
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18. A method for providing a memory in a programmable logic device comprising the steps of:
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receiving one or more inputs to said memory from a first bus and a second bus;
presenting one or more outputs from said memory to said first bus and said second bus; and
operating said memory in one or more modes in response to one or more control signals generated by said programmable logic device.
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Specification
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Current AssigneeMonterey Research, LLC (Vector Capital Corporation)
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsLacey, Timothy M., Johnson, David L.
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Primary Examiner(s)Tokar, Michael
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Assistant Examiner(s)CHO, JAMES HYONCHOL
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Application NumberUS10/024,093Time in Patent Office406 DaysField of Search326/40, 326/41, 326/47, 326/37-38US Class Current326/40CPC Class CodesH03K 19/1776 for memories
