Mixer structure and method for using same

• US 6,512,408 B2
• Filed: 11/06/2001
• Issued: 01/28/2003
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Jeong, Deog-Kyoon, Lee, Kyeongho
• Primary Examiner(s): Le, Dinh Thanh
• Application Number:
  US09/985,897
• Publication Number:
  US 20020030529A1
• Time in Patent Office: 448 Days
• Field of Search: 327/355, 327/356, 327/357, 327/361, 327/359, 327/113, 455/333, 455/326
• US Class Current: 327/359
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03K 9/00 Demodulating pulses which have been modulated with a continuously-variable signal
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

Claims

1. A circuit, comprising:

a multi-phase mixer that receives a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a second frequency,

wherein the multi-phase mixer combines the plurality of first clock signals to generate a plurality of local oscillator signals having the second frequency, and wherein the multi-phase mixer multiplies the plurality of local oscillator signals with input signals to provide output signals at output terminals.

2. The circuit of claim 1, wherein the input signals include an I-channel signal and a Q-channel signal, and wherein the multi-phase mixer multiplies the I-channel with one of the plurality of local oscillator signals and multiplies the Q-channel signal with another of the plurality of local oscillator signals.

3. The circuit of claim 1, further comprising a clock generator that receives a reference signal having a reference frequency and generates the plurality of first clock signals, wherein the clock generator includes a plurality of delay cells coupled in series to provide the plurality of first clock signals having different phases, and wherein the input signals are at the reference frequency.

4. The circuit of claim 1, wherein said multi-phase mixer comprises:

a load circuit coupled to a first prescribed voltage;

a switch array coupled to the load circuit at terminals providing the output signals, wherein the switch array receives the plurality of first clock signals from the clock generator and outputs the local oscillator signals; and

an input block coupled to the switch array, wherein the input block receives the input signals and outputs corresponding signals for the switch array.

5. The circuit of claim 4, wherein said multi-phase mixer further comprises a bias transistor between the input block and the switch array.

6. The circuit of claim 4, wherein the load circuit comprises:

first and second transistors coupled by first electrodes to the first prescribed voltage, wherein the first and second transistors have control electrodes coupled together;

a first load resistor coupled between the control electrode and a second electrode of the first transistor; and

a second load resistor coupled between the control electrode and a second electrode of the second transistor.

7. The circuit of claim 4, wherein the switch array comprises:

a first switch network coupled to receive a first group of the first clock signals and coupled to the load circuit to output a corresponding first local oscillator signal; and

a second switch network coupled to receive a second group of the first clock signals and coupled to the load circuit to output a corresponding second local oscillator signal.

8. The circuit of claim 7, wherein each of said first and second switch networks comprises a plurality of switches coupled to each other in parallel.

9. The circuit of claim 8, wherein each of said plurality of switches comprises a plurality of transistors coupled in series.

10. The circuit of claim 9, wherein each of the plurality of switches comprises:

first and third transistors coupled in series between a first node and a second node; and

second and fourth transistors coupled in series between the first node and the second node, wherein control electrodes of the first and fourth electrodes receive a first control signal and control electrodes of the second and third transistors receive a second control signal.

11. The circuit of claim 10, wherein second electrodes of the first and third electrodes are coupled together, wherein first electrodes of the first and second transistors are coupled to the first node, wherein first electrodes of the third and fourth transistors are coupled together, wherein second electrodes of the second and fourth transistors are coupled together, and wherein the first and second control signals are different ones of the first clock signals.

12. The circuit of claim 8, wherein each of the plurality of switches coupled in parallel includes first and second plurality of transistors coupled in series, wherein each of the plurality of switches receives a different pair of the plurality of first clock signals as its respective control signals.

13. The circuit of claim 4, wherein the switch array combines the plurality of first clock signals to generate the plurality of local oscillator signals having the second frequency substantially the same as the reference frequency and, wherein the input signals have the reference frequency and the output signals are baseband.

14. The circuit of claim 1, wherein the multi-phase mixer includes a switch array coupled to terminals providing the output signals, wherein the switch array receives the plurality of first clock signals and outputs the local oscillator signals.

15. The circuit of claim 14, wherein the switch array includes a plurality of transistor units coupled to each other in parallel, each transistor unit receiving at least one of the plurality of first clock signals as a respective control signal.

16. The circuit of claim 4, wherein the input block receives input voltages of the input signals and outputs corresponding current signals to the switch array.

17. The circuit of claim 16, wherein the input block is a transistor having a gate that receives the input signals, a first electrode coupled to a second prescribed voltage and a second electrode for outputting the corresponding current signals to the switch array.

18. The circuit of claim 1, where in the multi-phase mixer comprises:

a differential amplifying circuit for receiving the input signals and outputting the output signals; and

a combining circuit coupled to the differential amplifying circuit for receiving the plurality of first clock signals and outputting the local oscillator signals.

19. A method for processing input signals, comprising:

generating a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency of an input signal;

combining the plurality of first clock signals to generate a plurality of local oscillator signals having a second frequency higher than the first frequency; and

mixing the plurality of local oscillator signals with the input signal to provide an output signal.

20. The method of claim 19, wherein the output signal is at a baseband frequency.