Extended range variable gain amplifier
First Claim
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1. A method of varying the gain of an amplifier,wherein the amplifier is comprised of an amplifier array and an automatic gain control (AGC) logic decoder, wherein the amplifier array is further comprised of “
- n”
amplifier circuit assemblies, where “
n”
is a positive integer, wherein an “
ith”
amplifier circuit assembly of the “
n”
amplifier circuit assemblies has an information input, a control input and one or more amplifier outputs, and the AGC logic decoder is further comprised of “
n”
AGC amplifiers and “
n”
logic circuits, wherein an ith AGC amplifier of the “
n”
AGC amplifiers has two or more inputs and one or more outputs, each output being an AGC control signal, and an ith logic circuit of the “
n”
logic circuits has one or more logic inputs and one or more logic outputs, wherein a first logic output is an amplifier control signal and a second logic output is a shifting signal;
the method comprising the steps of;
(1) routing an AGC signal to a first input of the ith AGC amplifier;
(2) comparing said AGC signal to an ith scaled reference voltage, said ith scaled reference voltage being received at a second input of the ith AGC amplifier for all i between 1 and (n−
q), inclusive, where q is a positive integer less than n;
(3) for all “
i”
between 1 and (n−
q), inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is a first logic level if said AGC signal is greater than said ith scaled reference voltage, and is a second logic level if said AGC signal is less than said ith scaled reference voltage;
(4) for all “
i”
between (n−
q+1) and “
n”
, inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is at said first logic level;
(5) routing said ith AGC control signal to a first logic input of the ith logic circuit;
(6) generating, in the ith logic circuit, the ith shifting signal;
(7) for all “
i”
between 1 and “
m”
, inclusive, where “
m”
is a positive integer less than “
n”
, routing the ith shifting signal to a second logic input of the “
jth”
logic circuit, where j=i+p where p is a positive integer equal to (n−
m);
(8) generating, in the ith logic circuit, the ith amplifier control signal, wherein the ith amplifier control signal is a first control level when the ith amplifier circuit assembly is to be turned “
on”
, and is a second control level when the ith amplifier circuit assembly is to be turned “
off”
;
(9) routing the ith amplifier control signal to the control input of the ith amplifier circuit assembly;
(10) for all “
i”
between 1 and “
p”
, inclusive, accepting, at the information input of the ith amplifier circuit, an input signal;
(11) for all “
i”
between (p+1) and “
n”
, inclusive, accepting, at the information input of the ith amplifier circuit, an ith attenuated input signal;
(12) for all “
i”
between 1 and “
p”
, inclusive, amplifying said input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal;
(13) for all “
i”
between (p+1) and “
n”
, inclusive, amplifying said attenuated input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal; and
(14) outputting, from the amplifier output of the ith amplifier circuit, an ith amplifier output signal, wherein said ith amplifier output signal is said ith amplified signal when the ith amplifier control signal is at said first control level, and is a null signal when the ith amplifier control signal is at said second control level.
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Abstract
An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.
38 Citations
40 Claims
-
1. A method of varying the gain of an amplifier,
wherein the amplifier is comprised of an amplifier array and an automatic gain control (AGC) logic decoder, wherein the amplifier array is further comprised of “ - n”
amplifier circuit assemblies, where “
n”
is a positive integer,wherein an “
ith”
amplifier circuit assembly of the “
n”
amplifier circuit assemblies has an information input, a control input and one or more amplifier outputs, andthe AGC logic decoder is further comprised of “
n”
AGC amplifiers and “
n”
logic circuits,wherein an ith AGC amplifier of the “
n”
AGC amplifiers has two or more inputs and one or more outputs, each output being an AGC control signal, andan ith logic circuit of the “
n”
logic circuits has one or more logic inputs and one or more logic outputs, wherein a first logic output is an amplifier control signal and a second logic output is a shifting signal;
the method comprising the steps of;
(1) routing an AGC signal to a first input of the ith AGC amplifier;
(2) comparing said AGC signal to an ith scaled reference voltage, said ith scaled reference voltage being received at a second input of the ith AGC amplifier for all i between 1 and (n−
q), inclusive, where q is a positive integer less than n;
(3) for all “
i”
between 1 and (n−
q), inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is a first logic level if said AGC signal is greater than said ith scaled reference voltage, and is a second logic level if said AGC signal is less than said ith scaled reference voltage;
(4) for all “
i”
between (n−
q+1) and “
n”
, inclusive, generating an ith AGC control signal from the ith AGC amplifier, wherein the ith AGC control signal is at said first logic level;
(5) routing said ith AGC control signal to a first logic input of the ith logic circuit;
(6) generating, in the ith logic circuit, the ith shifting signal;
(7) for all “
i”
between 1 and “
m”
, inclusive, where “
m”
is a positive integer less than “
n”
, routing the ith shifting signal to a second logic input of the “
jth”
logic circuit, where j=i+p where p is a positive integer equal to (n−
m);
(8) generating, in the ith logic circuit, the ith amplifier control signal, wherein the ith amplifier control signal is a first control level when the ith amplifier circuit assembly is to be turned “
on”
, and is a second control level when the ith amplifier circuit assembly is to be turned “
off”
;
(9) routing the ith amplifier control signal to the control input of the ith amplifier circuit assembly;
(10) for all “
i”
between 1 and “
p”
, inclusive, accepting, at the information input of the ith amplifier circuit, an input signal;
(11) for all “
i”
between (p+1) and “
n”
, inclusive, accepting, at the information input of the ith amplifier circuit, an ith attenuated input signal;
(12) for all “
i”
between 1 and “
p”
, inclusive, amplifying said input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal;
(13) for all “
i”
between (p+1) and “
n”
, inclusive, amplifying said attenuated input signal when the ith amplifier control signal is at said first control level, thereby creating an ith amplified signal; and
(14) outputting, from the amplifier output of the ith amplifier circuit, an ith amplifier output signal, wherein said ith amplifier output signal is said ith amplified signal when the ith amplifier control signal is at said first control level, and is a null signal when the ith amplifier control signal is at said second control level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
(15) for all “
i”
between 1 and “
n”
, inclusive, combining all said ith amplifier output signals, thereby creating a combined amplified signal; and
(16) determining, from said combined amplified signal, said AGC signal.
- n”
-
3. The method of claim 2, further comprising the step of:
(17) demodulating said combined amplified signal.
-
4. The method of claim 1, wherein “
- n”
is 35.
- n”
-
5. The method of claim 4, wherein “
- m”
is 25 and “
p”
is 10.
- m”
-
6. The method of claim 4, wherein “
- q”
is 3.
- q”
-
7. The method of claim 4, wherein “
- q”
is 2.
- q”
-
8. The method of claim 4, wherein “
- q”
is 1.
- q”
-
9. The method of claim 1, wherein said first logic level is a logic “
- 1” and
said second logic level is a logic “
0”
.
- 1” and
-
10. The method of claim 1, wherein said first control level is a logic “
- 1” and
said second control level is a logic “
0”
.
- 1” and
-
11. The method of claim 1, wherein said input signal is a cable TV signal.
-
12. The method of claim 1, wherein said input signal is routed to a resistor ladder, the resistor ladder having “
- m”
nodes, wherein, for “
i”
between (p+1) and “
n”
, inclusive, at an ith node said input signal has been attenuated to be said ith attenuated input signal.
- m”
-
13. A system for controlling the gain of an amplifier, comprising:
-
(a) a plurality of automatic gain control (AGC) amplifiers, a corresponding plurality of logic circuits, and a corresponding plurality of amplifier circuit assemblies;
wherein;
(b) each of said plurality of AGC amplifiers has a first AGC input accepting an AGC signal;
each of said plurality of AGC amplifiers has a second AGC input accepting a comparison signal; and
each of said plurality of AGC amplifiers has an AGC output outputting an AGC control signal, said AGC control signal being at a first logic level when said AGC signal is equal to or greater than said corresponding comparison signal, and being at a second logic level when said AGC signal is less than said corresponding comparison signal,(i) wherein, for AGC amplifier number 1 through AGC amplifier number (n−
q), inclusive, said comparison signal is a scaled reference voltage wherein the scaled reference voltage at the ith AGC amplifier is greater than the scaled reference voltage at the (i+1)th AGC amplifier, where “
n”
is a positive integer greater than 10, and “
q”
is a positive integer less than “
n”
, and(ii) for AGC amplifier number (n−
q+1) through AGC amplifier number “
n”
, inclusive, said comparison signal is an electrical ground;
(c) each of said plurality of logic circuits has a first logic input accepting said AGC control signal;
logic circuit number (p+1) through logic circuit number “
n”
, inclusive, has a second logic input accepting an input logic shifting signal;
each of said plurality of logic circuits has a first logic output outputting an output logic shifting signal, wherein said output logic shifting signal from logic circuit number 1 through logic circuit number (n−
p), inclusive, is said input logic shifting signal for logic circuit number (p+1) through logic circuit number “
n”
, inclusive, respectively; and
each of said plurality of logic circuits has a second logic output outputting an amplifier control signal, wherein said amplifier control signal is at a first control level when said amplifier circuit assembly corresponding to said logic circuit is to be turned “
on”
, and at a second control level when said amplifier circuit assembly corresponding to said logic circuit is to be turned “
off”
, such that no more than “
p”
amplifier control signals are to be at said first control level at any time, wherein “
p”
is a positive integer less than “
n”
;
(d) each of said plurality of amplifier circuit assemblies has a control input accepting a corresponding amplifier control signal;
each of said plurality of amplifier circuit assemblies has a signal input, wherein, for amplifier circuit assembly number 1 through amplifier circuit assembly number “
p”
, inclusive, said signal input accepts an information signal, and for amplifier circuit assembly number (p+1) through amplifier circuit assembly number “
n”
, inclusive, said signal input accepts an attenuated information signal, wherein attenuated information signal “
i”
is less attenuated than attenuated information signal (i+1); and
each of said plurality of amplifier circuit assemblies has an amplified output, wherein, for every amplifier circuit assembly receiving an amplifier control signal at said first control level, said amplifier output is an amplified signal, and for every amplifier circuit assembly receiving an amplifier control signal at said second control level, said amplifier output is a null signal; and
(e) each said amplified output is combined to form a combined amplified signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. An amplifier array, comprising:
-
an input node;
a first set of amplifiers, arranged in a parallel fashion, and having their inputs tied together at said input node;
a resistor ladder coupled between said input node and ground; and
a second set of amplifiers, having their inputs tied to corresponding taps on said resistor ladder;
wherein outputs of said first set of amplifiers and outputs of said second set of amplifier are summed together at an output the amplifier array;
wherein gain for the amplifier array is adjusted by sequentially turning off one or more amplifiers in said first set of amplifiers, and sequentially turning on one or more amplifiers in said second set of amplifiers that correspond to said one or more amplifiers in said first set of amplifiers that are turned off. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 33, 34, 35, 36, 37, 38, 39, 40)
-
-
32. The amplifier array of 29, wherein said amplifier control signal causes said corresponding amplifier to operate linearly when a difference between said first voltage and said second voltage is less than a threshold.
Specification