Nonvolatile semiconductor memory
First Claim
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1. A nonvolatile semiconductor memory comprising:
- a memory cell array having a memory cell for programming data using an F-N tunneling current;
a bit line connected to the memory cell;
a sense amplifier connected to said bit line and having a latch function; and
means for, when data are to be simultaneously programmed in memory cells corresponding to one page, which are connected to a selected control gate line, applying a first potential to wells in which the memory cells of one page are formed, a second potential to a control gate of each of the memory cells of one page, the first potential to a bit line connected to a selected memory cell of the memory cells of one page, for which programming is to be executed, and an intermediate potential between the first and second potentials to a bit line connected to an unselected memory cell of the memory cells of one page, for which programming is not to be executed.
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Abstract
A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.
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Citations
1 Claim
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1. A nonvolatile semiconductor memory comprising:
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a memory cell array having a memory cell for programming data using an F-N tunneling current;
a bit line connected to the memory cell;
a sense amplifier connected to said bit line and having a latch function; and
means for, when data are to be simultaneously programmed in memory cells corresponding to one page, which are connected to a selected control gate line, applying a first potential to wells in which the memory cells of one page are formed, a second potential to a control gate of each of the memory cells of one page, the first potential to a bit line connected to a selected memory cell of the memory cells of one page, for which programming is to be executed, and an intermediate potential between the first and second potentials to a bit line connected to an unselected memory cell of the memory cells of one page, for which programming is not to be executed.
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Specification
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Current AssigneeJunichi Miyamoto, Koji Sakui
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Original AssigneeJunichi Miyamoto, Koji Sakui
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InventorsMiyamoto, Junichi, Sakui, Koji
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Primary Examiner(s)Elms, Richard
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Assistant Examiner(s)PHUNG, ANH K
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Application NumberUS09/921,570Publication NumberTime in Patent Office540 DaysField of Search365/189.05, 365/238.5, 365/185.01, 365/185.05, 365/185.11, 365/185.29, 365/185.33US Class Current365/189.05CPC Class CodesG11C 16/0433 comprising cells containing...G11C 16/10 Programming or data input c...
