Matched filter bank

• US 6,512,785 B1
• Filed: 02/11/1999
• Issued: 01/28/2003
• Est. Priority Date: 02/12/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: YOZAN, Inc.
• Inventors: Suzuki, Kunihiko, Zhang, Xiaoxing, Tomatsu, Takashi, Zhou, Xuping, Zhou, Changming
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US09/247,828
• Time in Patent Office: 1,447 Days
• Field of Search: 375/142, 375/143, 375/150, 375/152, 375/343, 708/314, 370/320, 370/335, 370/342, 370/441
• US Class Current: 375/143
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects

Abstract

A matched filter bank including a plurality of matched filters and a sampling and holding units commonly used by the total matched filters. Therefore, the circuit size is diminished.

An inverting amplifier for the matched filter with a variable gain includes an input capacitance, an inverting amplifier connected to an output of the input capacitance, and a plurality of feedback capacitances connected between an input and output of the inverting amplifier. A plurality of switches are connected to input side of the feedback capacitances for alternatively connecting the feedback capcitanec to the input of the inverting amplifier or a reference voltage. The feedback capacitances connected to the reference voltage are invalid with respect to a composite capacitance of the feedback capacitance and have no influence to the amplifier.

Claims

1. A matched filter bank comprising:

a sampling and holding unit for sampling and holding successive input signals of a number of “

m”

(m;

integer not less than

     2);

a plurality of PN code registers of a number of “

n”

(n;

integer not less than

     2), each said PN code register including a plurality of stages of number of “

m”

for storing coefficient data, each said PN code register being a shift register with circulation;

a plurality of groups of multiplication circuits of said number of “

n”

corresponding to said PN code registers, each said group including a plurality of multiplication circuits of said number of “

m”

corresponding to said stages of each said PN code register, each said multiplication circuit multiplying an output of one of said sampling and holding circuit and an output of one of said PN code register; and

one or more adders for adding selectively outputs of said multiplication circuits of a number corresponding to a length of said coefficient data.

2. A matched filter bank as claimed in claim 1, further comprising:

a mask register of “

m”

stages which stores control signals for selecting said outputs of said multiplication circuits corresponding to said length of said coefficient data; and

a plurality of multiplexers of said number of “

m′

”

corresponding to said multiplication circuits of said number of “

m”

, each said multiplexer selectively outputting said output of said corresponding multiplication circuit or “

0”

,

whereby said outputs from said multiplication circuits are selectively added corresponding to said length of said coefficient data.

3. A matched filter bank as claimed in claim 1, said sampling and holding unit comprising a plurality of sampling and holding circuits of said number of “

m”

.

4. A matched filter bank as claimed in claim 1, wherein said sampling and holding unit is a sampling shift register of a plurality of stages of said number of “

m”

.

5. A matched filter bank as claimed in claim 1, further comprising:

a mask register of “

m”

stages which stores control signals for selecting said outputs of said multiplication circuits corresponding to said length of said coefficient data; and

a multiplexer which selectively outputs one or more of said outputs among said “

m”

number of multiplication outputs to said adder according to said control signals in said mask register.

6. A matched filter bank as claimed in claim 1, further comprising an input PN code register corresponding to one or more of said PN code registers, each of which stores said coefficient data to be stored in said PN code registers in a next symbol period, and transfers said coefficient data parallelly to said corresponding PN code registers just before said next symbol period.

7. A matched filter bank as claimed in claim 1, further comprising an input mask register corresponding to said mask register, which stores said control signals to be stored in said mask register in a next symbol period, and transfers said control signals parallelly to said mask register just before said next symbol period.

8. A matched filter bank as claimed in claim 6, said input PN register comprising a plurality stages parallel latched of said number of “

m”

.

9. A matched filter bank as claimed in claim 7, said input mask register comprising a plurality stages parallel latched of said number of “

m”

.

10. A matched filter bank as claimed in claim 1, further comprising a sampling and holding control circuit which controls said sampling and holding unit.

11. A matched filter bank as claimed in claim 6 or 10, wherein said sampling and holding control circuit controls said input PN code register so that said coefficient data is input to said input PN code register synchronously to a timing when said sampling and holding unit samples and holds said input signal.

12. A matched filter bank as claimed in claim 7 or 10, wherein said sampling and holding control circuit controls said input mask register so that said control signals are input to said input mask register synchronously to a timing when said sampling and holding unit samples and holds said input signal.

13. A matched filter bank as claimed in claim 1, wherein a number of said adders is said number “

n”

corresponding to said “

n”

number of said groups of said multiplication circuits, and each said adder adds said outputs of said corresponding multiplication circuit of a number corresponding a length of said coefficient data from “

m”

number of said outputs of said corresponding multiplication circuit.

14. A matched filter bank as claimed in claim 1, wherein a number of said adders is one, which is connected to said total groups of multiplication circuits through a multiplexer which selectively connects one of said groups to said adder in a time sharing manner.

15. A matched filter bank as claimed in claim 1, further comprising a a plurality of registers corresponding to said groups of multiplication circuits, and a selector for connecting said output of said adder to one of said registers selectively.

16. A matched filter bank as claimed in claim 1, each said multiplication circuit comprising:

one or more of input capacitances having inputs and outputs which are connected at their input to an input voltage;

an inverting amplifier having input and output which is connected at its input to said outputs of said input capasitances;

one or more of feedback capacitances having inputs and outputs which are connected at their outputs to said output of said inverting amplifier; and

one or more of switched for connecting said outputs of one or more of said input capacitances, or said inputs of one or more of said feedback capacitances to said input of said inverting amplifier or to a reference voltage.

17. A matched filter bank as claimed in claim 16, wherein a plurality of said input capacitances are provided, and said switches are a plurality of input switches corresponding to said input capacitances, each said input switch connecting said output of said corresponding input capacitance to said input of said inverting amplifier or to a reference voltage.

18. A matched filter bank as claimed in claim 16, wherein a plurality of said feedback capacitances are provided, and said switches are a plurality of feedback switches corresponding to said feedback capacitances, each said feedback switch connecting said input of said corresponding feedback capacitance to said input of said inverting amplifier or to a reference voltage.